View CY7C64013_136097.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

C66011
CY7C64013 CY7C64113
CY7C64013 CY7C64113 Full-Speed USB (12 Mbps) Function
Cypress Semiconductor Corporation Document #: 38-08001 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised September 7, 2001
CY7C64013 CY7C64113
TABLE OF CONTENTS 1.0 FEATURES ..................................................................................................................................... 5 2.0 FUNCTIONAL OVERVIEW ............................................................................................................. 6 3.0 PIN CONFIGURATIONS ................................................................................................................. 8 4.0 PRODUCT SUMMARY TABLES .................................................................................................... 9 4.1 Pin Assignments ........................................................................................................................... 9 4.2 I/O Register Summary ................................................................................................................... 9 4.3 Instruction Set Summary ............................................................................................................ 11 5.0 PROGRAMMING MODEL ............................................................................................................. 12 5.1 14-Bit Program Counter (PC) ...................................................................................................... 12
5.1.1 Program Memory Organization ......................................................................................................... 13
5.2 8-Bit Accumulator (A) .................................................................................................................. 13 5.3 8-Bit Temporary Register (X) ...................................................................................................... 13 5.4 8-Bit Program Stack Pointer (PSP) ............................................................................................ 14
5.4.1 Data Memory Organization ................................................................................................................ 14
5.5 8-Bit Data Stack Pointer (DSP) ................................................................................................... 14 5.6 Address Modes ............................................................................................................................ 15
5.6.1 Data (Immediate) ................................................................................................................................. 15 5.6.2 Direct ................................................................................................................................................... 15 5.6.3 Indexed ................................................................................................................................................15
6.0 CLOCKING .................................................................................................................................... 15 7.0 RESET ........................................................................................................................................... 16 7.1 Power-On Reset (POR) ................................................................................................................ 16 7.2 Watch Dog Reset (WDR) ............................................................................................................. 16 8.0 SUSPEND MODE .......................................................................................................................... 17 9.0 GENERAL-PURPOSE I/O (GPIO) PORTS ................................................................................... 17 9.1 GPIO Configuration Port ............................................................................................................. 18 9.2 GPIO Interrupt Enable Ports ....................................................................................................... 19 10.0 DAC PORT .................................................................................................................................. 20 10.1 DAC Isink Registers .................................................................................................................. 20 10.2 DAC Port Interrupts ................................................................................................................... 21 11.0 12-BIT FREE-RUNNING TIMER ................................................................................................. 21 11.1 Timer (LSB) ................................................................................................................................ 21 11.2 Timer (MSB) ................................................................................................................................ 21 12.0 I2C AND HAPI CONFIGURATION REGISTER ......................................................................... 22 13.0 I2C COMPATIBLE CONTROLLER ............................................................................................. 23 14.0 HARDWARE ASSISTED PARALLEL INTERFACE (HAPI) ....................................................... 24 15.0 PROCESSOR STATUS AND CONTROL REGISTER ............................................................... 25 16.0 INTERRUPTS .............................................................................................................................. 26 16.1 16.2 16.3 16.4 Interrupt Vectors ........................................................................................................................ 27 Interrupt Latency ....................................................................................................................... 28 USB Bus Reset Interrupt ........................................................................................................... 28 Timer Interrupt ........................................................................................................................... 29
Page 2 of 48
Document #: 38-08001 Rev. **
CY7C64013 CY7C64113
16.5 16.6 16.7 16.8 USB Endpoint Interrupts ........................................................................................................... 29 DAC Interrupt ............................................................................................................................. 29 GPIO/HAPI Interrupt .................................................................................................................. 29 I2C Interrupt ................................................................................................................................ 30
17.0 USB OVERVIEW ......................................................................................................................... 30 17.1 USB Serial Interface Engine (SIE) ............................................................................................ 30 17.2 USB Enumeration ...................................................................................................................... 31 17.3 USB Upstream Port Status and Control .................................................................................. 31 18.0 USB SERIAL INTERFACE ENGINE OPERATION .................................................................... 32 18.1 18.2 18.3 18.4 18.5 18.6 USB Device Address ................................................................................................................. 32 USB Device Endpoints .............................................................................................................. 32 USB Control Endpoint Mode Register ..................................................................................... 32 USB Non-Control Endpoint Mode Registers ........................................................................... 33 USB Endpoint Counter Registers ............................................................................................ 33 Endpoint Mode/Count Registers Update and Locking Mechanism ...................................... 34
19.0 USB MODE TABLES .................................................................................................................. 36 20.0 SAMPLE SCHEMATIC ................................................................................................................ 40 21.0 ABSOLUTE MAXIMUM RATINGS ............................................................................................. 41 22.0 ELECTRICAL CHARACTERISTICS ........................................................................................... 41 23.0 SWITCHING CHARACTERISTICS ............................................................................................. 43 24.0 ORDERING INFORMATION ....................................................................................................... 46 25.0 PACKAGE DIAGRAMS .............................................................................................................. 46 LIST OF FIGURES Figure 5-1. Program Memory Space with Interrupt Vector Table .................................................. 13 Figure 6-1. Clock Oscillator On-Chip Circuit ................................................................................... 15 Figure 7-1. Watch Dog Reset (WDR) ................................................................................................ 16 Figure 9-1. Block Diagram of a GPIO Pin ........................................................................................ 17 Figure 9-2. Port 0 Data 0x00 (read/write) ......................................................................................... 18 Figure 9-3. Port 1 Data 0x01 (read/write) ......................................................................................... 18 Figure 9-4. Port 2 Data 0x02 (read/write) ......................................................................................... 18 Figure 9-5. Port 3 Data 0x03 (read/write) ......................................................................................... 18 Figure 9-6. GPIO Configuration Register 0x08 (read/write) ........................................................... 19 Figure 9-7. Port 0 Interrupt Enable 0x04 (read/write) ..................................................................... 19 Figure 9-8. Port 1 Interrupt Enable 0x05 (read/write) ..................................................................... 19 Figure 9-9. Port 2 Interrupt Enable 0x06 (read/write) ..................................................................... 19 Figure 9-10. Port 3 Interrupt Enable 0x07 (read/write) ................................................................... 19 Figure 10-1. Block Diagram of a DAC Pin ........................................................................................ 20 Figure 10-2. DAC Port Data 0x30 (read/write) ................................................................................. 20 Figure 10-3. DAC Port Isink 0x38 to 0x3F (write only) .................................................................... 20 Figure 10-4. DAC Port Interrupt Enable 0x31 (write only) .............................................................. 21 Figure 10-5. DAC Port Interrupt Polarity 0x32 (write only) ............................................................ 21 Figure 11-1. Timer Register 0x24 (read only) .................................................................................. 21 Figure 11-2. Timer Register 0x25 (read only) .................................................................................. 21 Figure 11-3. Timer Block Diagram .................................................................................................... 22 Figure 12-1. HAPI/I2C Configuration Register 0x09 (read/write) ................................................... 22
Document #: 38-08001 Rev. ** Page 3 of 48
CY7C64013 CY7C64113
Figure 13-1. I2C Data Register 0x29 (separate read/write registers) ............................................. 23 Figure 13-2. I2C Status and Control Register 0x28 (read/write) .................................................... 23 Figure 15-1. Processor Status and Control Register 0xFF ............................................................ 25 Figure 16-1. Global Interrupt Enable Register 0x20 (read/write) ................................................... 26 Figure 16-2. USB Endpoint Interrupt Enable Register 0x21 (read/write) ...................................... 26 Figure 16-3. Interrupt Controller Functional Diagram .................................................................... 27 Figure 16-4. Interrupt Vector Register 0x23 (read only) ................................................................. 28 Figure 16-5. GPIO Interrupt Structure .............................................................................................. 29 Figure 17-1. USB Status and Control Register 0x1F (read/write) .................................................. 31 Figure 18-1. USB Device Address Register 0x10 (read/write) ....................................................... 32 Figure 18-2. USB Device Endpoint Zero Mode Register 0x12 (read/write) ................................... 32 Figure 18-3. USB Non-Control Device Endpoint Mode Registers 0x14, 0x16, 0x42, 0x44, (read/write) ............................................................................................... 33 Figure 18-4. USB Endpoint Counter Registers 0x11, 0x13, 0x15, 0x41, 0x43 (read/write) .......... 33 Figure 18-5. Token/Data Packet Flow Diagram ............................................................................... 35 Figure 22-1. Clock Timing ................................................................................................................. 44 Figure 22-2. USB Data Signal Timing ............................................................................................... 44 Figure 22-3. HAPI Read by External Interface from USB Microcontroller .................................... 44 Figure 22-4. HAPI Write by External Device to USB Microcontroller ............................................ 45 LIST OF TABLES Table 4-1. Pin Assignments ................................................................................................................ 9 Table 4-2. I/O Register Summary ........................................................................................................ 9 Table 4-3. Instruction Set Summary ................................................................................................. 11 Table 9-1. Port Configurations ......................................................................................................... 18 Table 12-1. HAPI Port Configuration ................................................................................................ 22 Table 12-2. I2C Port Configuration ................................................................................................... 22 Table 13-1. I2C Status and Control Register Bit Definitions .......................................................... 23 Table 14-1. Port 2 Pin and HAPI Configuration Bit Definitions ..................................................... 25 Table 16-1. Interrupt Vector Assignments ....................................................................................... 28 Table 17-1. Control Bit Definition for Upstream Port ..................................................................... 31 Table 18-1. Memory Allocation for Endpoints ................................................................................ 32 Table 19-1. USB Register Mode Encoding ...................................................................................... 36 Table 19-2. Decode table for Table 19-3: "Details of Modes for Differing Traffic Conditions" ... 37 Table 19-3. Details of Modes for Differing Traffic Conditions ....................................................... 38
Document #: 38-08001 Rev. **
Page 4 of 48
CY7C64013 CY7C64113
1.0 Features
* Full-speed USB Microcontroller * 8-bit USB Optimized Microcontroller -- Harvard architecture -- 6-MHz external clock source -- 12-MHz internal CPU clock -- 48-MHz internal clock * Internal memory -- 256 bytes of RAM -- 8 KB of PROM (CY7C64013, CY7C64113) * Integrated Master/Slave I2C Compatible Controller (100 kHz) enabled through General-Purpose I/O (GPIO) pins * Hardware Assisted Parallel Interface (HAPI) for data transfer to external devices * I/O ports -- Three GPIO ports (Port 0 to 2) capable of sinking 7 mA per pin (typical) -- An additional GPIO port (Port 3) capable of sinking 12 mA per pin (typical) for high current requirements: LEDs -- Higher current drive achievable by connecting multiple GPIO pins together to drive a common output -- Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs -- A Digital to Analog Conversion (DAC) port with programmable current sink outputs is available on the CY7C64113 devices * * * * -- Maskable interrupts on all I/O pins 12-bit free-running timer with one microsecond clock ticks Watch Dog Timer (WDT) Internal Power-On Reset (POR) USB Specification Compliance -- Conforms to USB Specification, Version 1.1 -- Conforms to USB HID Specification, Version 1.1 -- Supports up to five user configured endpoints Up to four 8-byte data endpoints Up to two 32-byte data endpoints -- Integrated USB transceivers * Improved output drivers to reduce EMI * Operating voltage from 4.0V to 5.5V DC * Operating temperature from 0 to 70 degrees Celsius -- CY7C64013 available in 28-pin SOIC and 28-pin PDIP packages -- CY7C64113 available in 48-pin SSOP packages * Industry-standard programmer support
Document #: 38-08001 Rev. **
Page 5 of 48
CY7C64013 CY7C64113
2.0 Functional Overview
The CY7C64013 and CY7C64113 are 8-bit One Time Programmable microcontrollers that are designed for full-speed USB applications. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications. The CY7C64013 features 19 GPIO pins to support USB and other applications. The I/O pins are grouped into three ports (P0[7:0], P1[7:0], P3[7,2,0]) where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. There are 16 GPIO pins (Ports 0 and 1) which are rated at 7 mA typical sink current. Port 3 pins are rated at 12 mA typical sink current, a current sufficient to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Additionally, each GPIO can be used to generate a GPIO interrupt to the microcontroller. All of the GPIO interrupts share the same "GPIO" interrupt vector. Thirty-two GPIO pins (P0[7:0], P1[7:0], P2[7:0], P3[7:0]) and four Digital to Analog Conversion (DAC) pins (P4[7,2:0]) are available on the CY7C64113. Every DAC pin includes an integrated 14-k pull-up resistor. When a `1' is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven HIGH by the internal pull-up resistor. When a `0' is written to a DAC I/O pin, the internal pull-up resistor is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin can be used as an input with an internal pull-up by writing a `1' to the pin. The sink current for each DAC I/O pin can be individually programmed to one of 16 values using dedicated Isink registers. DAC bits P4[1:0] can be used as high-current outputs with a programmable sink current range of 3.2 to 16 mA (typical). DAC bits P4[7,2] have a programmable current sink range of 0.2 to 1.0 mA (typical). Multiple DAC pins can be connected together to drive a single output that requires more sink current capacity. Each I/O pin can be used to generate a DAC interrupt to the microcontroller. Also, the interrupt polarity for each DAC I/O pin is individually programmable. The microcontroller uses an external 6-MHz crystal and an internal oscillator to provide a reference to an internal PLL-based clock generator. This technology allows the customer application to use an inexpensive 6-MHz fundamental crystal that reduces the clock-related noise emissions (EMI). A PLL clock generator provides the 6-, 12-, and 48-MHz clock signals for distribution within the microcontroller. The CY7C64013 and CY7C64113 have 8 KB of PROM. These parts include power-on reset logic, a watch dog timer, and a 12-bit free-running timer. The power-on reset (POR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at PROM address 0x0000. The watch dog timer is used to ensure the microcontroller recovers after a period of inactivity. The firmware may become inactive for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs. The microcontroller can communicate with external electronics through the GPIO pins. An I2C compatible interface accommodates a 100-kHz serial link with an external device. There is also a Hardware Assisted Parallel Interface (HAPI) which can be used to transfer data to an external device. The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128-s and 1.024-ms. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read. The microcontroller supports 11 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus Reset interrupt, the 128-s (bit 6) and 1.024-ms (bit 9) outputs from the free-running timer, five USB endpoints, the DAC port, the GPIO ports, and the I2C compatible master mode interface. The timer bits cause an interrupt (if enabled) when the bit toggles from LOW `0' to HIGH `1.' The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB controller sends a packet to the USB host. The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be rising edge (`0' to `1') or falling edge (`1' to `0').
Document #: 38-08001 Rev. **
Page 6 of 48
CY7C64013 CY7C64113
.
Logic Block Diagram
6-MHz crystal
PLL
48 MHz Clock Divider 12 MHz PROM 8 KB 8-bit Bus Interrupt Controller
12-MHz 8-bit CPU
USB SIE
USB Transceiver
D+[0] Upstream D-[0] USB Port
RAM 256 byte
GPIO PORT 0
P0[7:0]
6 MHz 12-bit Timer
GPIO PORT 1
P1[2:0] P1[7:3] CY7C64113 only
Watch Dog Timer
GPIO/ HAPI PORT 2
P2[0,1,7] P2[2]; Latch_Empty P2[3]; Data_Ready P2[4]; STB P2[5]; OE P2[6]; CS
Power-On Reset
P3[2:0]
GPIO PORT 3
P3[7:3]
High Current Outputs
Additional High Current Outputs
DAC PORT
DAC[0] DAC[2] DAC[7] CY7C64113 only
I2C Interface
SCLK SDATA
*I2C compatible interface enabled by firmware through P2[1:0] or P1[1:0]
Document #: 38-08001 Rev. **
Page 7 of 48
CY7C64013 CY7C64113
3.0 Pin Configurations
TOP VIEW CY7C64013 28-pin SOIC
XTALOUT XTALIN VREF GND P3[1] D+[0] D-[0] P2[3] P2[5] P0[7] P0[5] P0[3] P0[1] P0[6] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC P1[1] P1[0] P1[2] P3[0] P3[2] GND P2[2] P2[4] P2[6] VPP P0[0] P0[2] P0[4] XTALOUT XTALIN VREF P1[1] GND P3[1] D+[0] D-[0] P2[3] P2[5] P0[7] P0[5] P0[3] P0[1]
CY7C64013 28-pin PDIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC P1[0] P1[2] P3[0] P3[2] P2[2] GND P2[4] P2[6] VPP P0[0] P0[2] P0[4] P0[6] XTALOUT XTALIN VREF P1[3] P1[5] P1[7] P3[1] D+[0] D-[0] P3[3] GND P3[5] P3[7] P2[1] P2[3] GND P2[5] P2[7] DAC[7] P0[7] P0[5] P0[3] P0[1] DAC[1]
CY7C64113 48-pin SSOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC P1[1] P1[0] P1[2] P1[4] P1[6] P3[0] P3[2] GND P3[4] NC P3[6] P2[0] P2[2] GND P2[4] P2[6] DAC[0] VPP P0[0] P0[2] P0[4] P0[6] DAC[2]
Document #: 38-08001 Rev. **
Page 8 of 48
CY7C64013 CY7C64113
4.0
4.1
Product Summary Tables
Pin Assignments
Table 4-1. Pin Assignments Name D+[0], D-[0] P0 I/O I/O I/O 28-Pin SOIC 6, 7 P0[7:0] 10, 14, 11, 15, 12, 16, 13, 17 P1[2:0] 25, 27, 26 P2[6:2] 19, 9, 20, 8, 21 P3[2:0] 23, 5, 24 28-Pin PDIP 7, 8 P0[7:0] 11, 15, 12, 16, 13, 17, 14, 18 P1[2:0] 26, 4, 27 P2[6:2] 20, 10, 21, 9, 23 P3[2:0] 24, 6, 25 48-Pin SSOP 7, 8 Description Upstream port, USB differential data.
P0[7:0] GPIO Port 0 capable of sinking 7 mA (typical). 20, 26, 21, 27, 22, 28, 23, 29 P1[7:0] 6, 43, 5, 44, 4, 45, 47, 46 GPIO Port 1 capable of sinking 7 mA (typical).
P1
I/O
P2
I/O
P2[7:0] GPIO Port 2 capable of sinking 7 mA (typical). HAPI 18, 32, 17, 33, is also supported through P2[6:2]. 15, 35, 14, 36 P3[7:0] GPIO Port 3, capable of sinking 12 mA (typical). 13, 37, 12, 39, 10, 41, 7, 42 DAC[7,2:0] 19, 25, 24, 31 DAC Port with programmable current sink outputs. DAC[1:0] offer a programmable range of 3.2 to 16 mA typical. DAC[7,2] have a programmable sink current range of 0.2 to 1.0 mA typical. 6-MHz crystal or external clock input. 6-MHz crystal out. Programming voltage supply, tie to ground during normal operation. Voltage supply. Ground. External 3.3V supply voltage for the differential data output buffers and the D+ pull-up. No Connect.
P3
I/O
DAC
I/O
XTALIN XTALOUT VPP VCC GND VREF NC
IN OUT IN IN IN IN
2 1 18 28 4, 22 3
2 1 19 28 5, 22 3
2 1 30 48 11, 16, 34, 40 3 38
4.2
I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X. All undefined registers are reserved. It is important not to write to reserved registers as this may cause an undefined operation or increased current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written with `0.' Table 4-2. I/O Register Summary Register Name Port 0 Data Port 1 Data Port 2 Data Port 3 Data Port 0 Interrupt Enable Port 1 Interrupt Enable Port 2 Interrupt Enable Port 3 Interrupt Enable Document #: 38-08001 Rev. ** I/O Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Read/Write R/W R/W R/W R/W W W W W GPIO Port 0 Data GPIO Port 1 Data GPIO Port 2 Data GPIO Port 3 Data Interrupt Enable for Pins in Port 0 Interrupt Enable for Pins in Port 1 Interrupt Enable for Pins in Port 2 Interrupt Enable for Pins in Port 3 Function Page 18 18 18 18 19 19 19 19 Page 9 of 48
CY7C64013 CY7C64113
Table 4-2. I/O Register Summary (continued) Register Name GPIO Configuration HAPI and I2C Configuration USB Device Address A EP A0 Counter Register EP A0 Mode Register EP A1 Counter Register EP A1 Mode Register EP A2 Counter Register EP A2 Mode Register USB Status & Control Global Interrupt Enable Endpoint Interrupt Enable Interrupt Vector Timer (LSB) Timer (MSB) WDT Clear I C Control & Status I C Data DAC Data DAC Interrupt Enable DAC Interrupt Polarity DAC Isink Reserved EP A3 Counter Register EP A3 Mode Register EP A4 Counter Register EP A4 Mode Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Processor Status & Control
2 2
I/O Address 0x08 0x09 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x1F 0x20 0x21 0x23 0x24 0x25 0x26 0x28 0x29 0x30 0x31 0x32 0x38-0x3F 0x40 0x41 0x42 0x43 0x44 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0xFF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R W R/W R/W R/W W W W R/W R/W R/W R/W
Function GPIO Port Configurations HAPI Width and I2C Position Configuration USB Device Address A USB Address A, Endpoint 0 Counter USB Address A, Endpoint 0 Configuration USB Address A, Endpoint 1 Counter USB Address A, Endpoint 1 Configuration USB Address A, Endpoint 2 Counter USB Address A, Endpoint 2 Configuration USB Upstream Port Traffic Status and Control Global Interrupt Enable USB Endpoint Interrupt Enables Pending Interrupt Vector Read / Clear Lower 8 Bits of Free-running Timer (1 MHz) Upper 4 Bits of Free-running Timer Watch Dog Timer Clear I C Status and Control I C Data DAC Data Interrupt Enable for each DAC Pin Interrupt Polarity for each DAC Pin Input Sink Current Control for each DAC Pin Reserved USB Address A, Endpoint 3 Counter USB Address A, Endpoint 3 Configuration USB Address A, Endpoint 4 Counter USB Address A, Endpoint 4 Configuration Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
2 2
Page 19 22 32 33 32 33 33 33 33 31 26 26 28 21 21 16 23 23 20 21 21 20 33 32 33 33
R/W
Microprocessor Status and Control Register
25
Document #: 38-08001 Rev. **
Page 10 of 48
CY7C64013 CY7C64113
4.3 Instruction Set Summary
Refer to the CYASM Assembler User's Guide for more details. Table 4-3. Instruction Set Summary MNEMONIC HALT ADD A,expr ADD A,[expr] ADD A,[X+expr] ADC A,expr ADC A,[expr] ADC A,[X+expr] SUB A,expr SUB A,[expr] SUB A,[X+expr] SBB A,expr SBB A,[expr] SBB A,[X+expr] OR A,expr OR A,[expr] OR A,[X+expr] AND A,expr AND A,[expr] AND A,[X+expr] XOR A,expr XOR A,[expr] XOR A,[X+expr] CMP A,expr CMP A,[expr] CMP A,[X+expr] MOV A,expr MOV A,[expr] MOV A,[X+expr] MOV X,expr MOV X,[expr] reserved XPAGE MOV A,X MOV X,A MOV PSP,A CALL JMP CALL JZ JNZ addr addr addr addr addr data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct index data direct operand opcode 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 40 41 60 50 - 5F 80-8F 90-9F A0-AF B0-BF 4 4 4 4 10 5 10 5 5 Page 11 of 48 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 4 6 7 5 7 8 4 5 6 4 5 cycles NOP INC A INC X INC [expr] INC [X+expr] DEC A DEC X DEC [expr] DEC [X+expr] IORD expr IOWR expr POP A POP X PUSH A PUSH X SWAP A,X SWAP A,DSP MOV [expr],A MOV [X+expr],A OR [expr],A OR [X+expr],A AND [expr],A AND [X+expr],A XOR [expr],A XOR [X+expr],A IOWX [X+expr] CPL ASL ASR RLC RRC RET DI EI RETI JC JNC JACC INDEX addr addr addr addr direct index direct index direct index direct index index acc x direct index acc x direct index address address MNEMONIC operand opcode 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 70 72 73 C0-CF D0-DF E0-EF F0-FF 4 4 4 7 8 4 4 7 8 5 5 4 4 5 5 5 5 5 6 7 8 7 8 7 8 6 4 4 4 4 4 8 4 4 8 5 5 7 14 cycles
Document #: 38-08001 Rev. **
CY7C64013 CY7C64113
5.0
5.1
Programming Model
14-Bit Program Counter (PC)
The 14-bit program counter (PC) allows access to up to 8 KB of PROM available with the CY7C64x13 architecture. The top 32 bytes of the ROM in the 8 Kb part are reserved for testing purposes. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. Typically, this is a jump instruction to a reset handler that initializes the application (see Interrupt Vectors on page 27). The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte "page" of sequential code should be an XPAGE instruction. The assembler directive "XPAGEON" causes the assembler to insert XPAGE instructions automatically. Because instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE to execute correctly. The address of the next instruction to be executed, the carry flag, and the zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack during a RETI instruction. Only the program counter is restored during a RET instruction. The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.
Document #: 38-08001 Rev. **
Page 12 of 48
CY7C64013 CY7C64113
5.1.1 Program Memory Organization after reset 14-bit PC Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A
Program execution begins here after a reset USB Bus Reset interrupt vector 128-s timer interrupt vector 1.024-ms timer interrupt vector USB address A endpoint 0 interrupt vector USB address A endpoint 1 interrupt vector USB address A endpoint 2 interrupt vector USB address A endpoint 3 interrupt vector USB address A endpoint 4 interrupt vector Reserved DAC interrupt vector GPIO interrupt vector I2C interrupt vector Program Memory begins here
0x1FDF
8 KB (-32) PROM ends here (CY7C64013, CY7C64113)
Figure 5-1. Program Memory Space with Interrupt Vector Table
5.2
8-Bit Accumulator (A)
The accumulator is the general-purpose register for the microcontroller.
5.3
8-Bit Temporary Register (X)
The "X" register is available to the firmware for temporary storage of intermediate results. The microcontroller can perform indexed operations based on the value in X. Refer to Section 5.6.3 for additional information.
Document #: 38-08001 Rev. **
Page 13 of 48
CY7C64013 CY7C64113
5.4 8-Bit Program Stack Pointer (PSP)
During a reset, the program stack pointer (PSP) is set to 0x00 and "grows" upward from this address. The PSP may be set by firmware, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control. The PSP is not readable by the firmware. During an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the PSP, then the PSP is incremented. The second byte is stored in memory addressed by the PSP, and the PSP is incremented again. The overall effect is to store the program counter and flags on the program "stack" and increment the PSP by two. The Return from Interrupt (RETI) instruction decrements the PSP, then restores the second byte from memory addressed by the PSP. The PSP is decremented again and the first byte is restored from memory addressed by the PSP. After the program counter and flags have been restored from stack, the interrupts are enabled. The overall effect is to restore the program counter and flags from the program stack, decrement the PSP by two, and re-enable interrupts. The Call Subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two. The Return from Subroutine (RET) instruction restores the program counter but not the flags from the program stack and decrements the PSP by two. 5.4.1 Data Memory Organization
The CY7C64x13 microcontrollers provide 256 bytes of data RAM. Normally, the SRAM is partitioned into four areas: program stack, user variables, data stack, and USB endpoint FIFOs. The following is one example of where the program stack, data stack, and user variables areas could be located. After reset 8-bit DSP 8-bit PSP (Move DSP[1]) Address 0x00
Program Stack Growth
8-bit DSP
user selected User variables
Data Stack Growth
USB FIFO space for five endpoints[2] 0xFF
5.5
8-Bit Data Stack Pointer (DSP)
The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads data from the memory location addressed by the DSP, then post-increments the DSP. During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM (address 0xFF). This writes data to the memory area reserved for USB endpoint FIFOs. Therefore, the DSP should be indexed at an appropriate memory location that does not compromise the Program Stack, user-defined memory (variables), or the USB endpoint FIFOs. For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are described in Section 18.2. Example assembly instructions to do this with two device addresses (FIFOs begin at 0xD8) are shown below: MOV A,20h ; Move 20 hex into Accumulator (must be D8h or less) SWAP A,DSP ; swap accumulator value into DSP register
Notes: 1. Refer to Section 5.5 for a description of DSP. 2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see Table 18-1.
Document #: 38-08001 Rev. **
Page 14 of 48
CY7C64013 CY7C64113
5.6 Address Modes
The CY7C64013 and CY7C64113 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. 5.6.1 Data (Immediate)
"Data" address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0xD8: * MOV A,0D8h This instruction requires two bytes of code where the first byte identifies the "MOV A" instruction with a data operand as the second byte. The second byte of the instruction is the constant "0xD8." A constant may be referred to by name if a prior "EQU" statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above: * DSPINIT: EQU 0D8h * MOV A,DSPINIT 5.6.2 Direct
"Direct" address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10: * MOV A,[10h] Normally, variable names are assigned to variable addresses using "EQU" statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above: * buttons: EQU 10h * MOV A,[buttons] 5.6.3 Indexed
"Indexed" address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the "X" register. Normally, the constant is the "base" address of an array of data and the X register contains an index that indicates which element of the array is actually addressed: * array: EQU 10h * MOV X,3 * MOV A,[X+array] This would have the effect of loading A with the fourth element of the SRAM "array" that begins at address 0x10. The fourth element would be at address 0x13.
6.0
Clocking
XTALOUT (pin 1)
XTALIN (pin 2) 30 pF
to internal PLL 30 pF
Figure 6-1. Clock Oscillator On-Chip Circuit The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to these pins. When using an external crystal, keep PCB traces between the chip leads and crystal as short as possible (less than 2 cm). A 6-MHz fundamental frequency parallel resonant crystal can be connected to these pins to provide a reference frequency for the internal PLL. The two internal 30-pF load caps appear in series to the external crystal and would be equivalent to a 15 pF load. Therefore, the crystal must have a required load capacitance of about 15-18 pF. A ceramic resonator does not allow the microcontroller to meet the timing specifications of full speed USB and therefore a ceramic resonator is not recommended with these parts. An external 6-MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open. Grounding the XTALOUT pin when driving XTALIN with an oscillator does not work because the internal clock is effectively shorted to ground. Document #: 38-08001 Rev. ** Page 15 of 48
CY7C64013 CY7C64113
7.0 Reset
The CY7C64x13 supports two resets: Power-On Reset (POR) and a Watch Dog Reset (WDR). Each of these resets causes: * all registers to be restored to their default states, * the USB Device Address to be set to 0, * all interrupts to be disabled, * the PSP and Data Stack Pointer (DSP) to be set to memory address 0x00. The occurrence of a reset is recorded in the Processor Status and Control Register, as described in Section 15.0. Bits 4 and 6 are used to record the occurrence of POR and WDR, respectively. Firmware can interrogate these bits to determine the cause of a reset. Program execution starts at ROM address 0x0000 after a reset. Although this looks like interrupt vector 0, there is an important difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto program stack. The firmware reset handler should configure the hardware before the "main" loop of code. Attempting to execute a RET or RETI in the firmware reset handler causes unpredictable execution results.
7.1
Power-On Reset (POR)
When VCC is first applied to the chip, the Power-On Reset (POR) signal is asserted and the CY7C64x13 enters a "semi-suspend" state. During the semi-suspend state, which is different from the suspend state defined in the USB specification, the oscillator and all other blocks of the part are functional, except for the CPU. This semi-suspend time ensures that both a valid VCC level is reached and that the internal PLL has time to stabilize before full operation begins. When the VCC has risen above approximately 2.5V, and the oscillator is stable, the POR is deasserted and the on-chip timer starts counting. The first 1 ms of suspend time is not interruptible, and the semi-suspend state continues for an additional 95 ms unless the count is bypassed by a USB Bus Reset on the upstream port. The 95 ms provides time for VCC to stabilize at a valid operating voltage before the chip executes code. If a USB Bus Reset occurs on the upstream port during the 95-ms semi-suspend time, the semi-suspend state is aborted and program execution begins immediately from address 0x0000. In this case, the Bus Reset interrupt is pending but not serviced until firmware sets the USB Bus Reset Interrupt Enable bit (bit 0 of register 0x20) and enables interrupts with the EI command. The POR signal is asserted whenever VCC drops below approximately 2.5V, and remains asserted until VCC rises above this level again. Behavior is the same as described above.
7.2
Watch Dog Reset (WDR)
The Watch Dog Timer Reset (WDR) occurs when the internal Watch Dog timer rolls over. Writing any value to the write-only Watch Dog Restart Register at address 0x26 clears the timer. The timer rolls over and WDR occurs if it is not cleared within tWATCH (8 ms minimum) of the last clear. Bit 6 of the Processor Status and Control Register is set to record this event (the register contents are set to 010X0001 by the WDR). A Watch Dog Timer Reset lasts for 2 ms, after which the microcontroller begins execution at ROM address 0x0000. tWATCH 2 ms
Last write to Watch Dog Timer Register
No write to WDT register, so WDR goes HIGH
Execution begins at Reset Vector 0x0000
Figure 7-1. Watch Dog Reset (WDR) The USB transmitter is disabled by a Watch Dog Reset because the USB Device Address Register is cleared (see Section 18.1). Otherwise, the USB Controller would respond to all address 0 transactions. It is possible for the WDR bit of the Processor Status and Control Register (0xFF) to be set following a POR event. The WDR bit should be ignored If the firmware interrogates the Processor Status and Control Register for a Set condition on the WDR bit and if the POR (bit 3 of register 0xFF) bit is set.
Document #: 38-08001 Rev. **
Page 16 of 48
CY7C64013 CY7C64113
8.0 Suspend Mode
The CY7C64x13 can be placed into a low-power state by setting the Suspend bit of the Processor Status and Control register. All logic blocks in the device are turned off except the GPIO interrupt logic and the USB receiver. The clock oscillator and PLL, as well as the free-running and Watch Dog timers, are shut down. Only the occurrence of an enabled GPIO interrupt or non-idle bus activity at a USB upstream or downstream port wakes the part out of suspend. The Run bit in the Processor Status and Control Register must be set to resume a part out of suspend. The clock oscillator restarts immediately after exiting suspend mode. The microcontroller returns to a fully functional state 1 ms after the oscillator is stable. The microcontroller executes the instruction following the I/O write that placed the device into suspend mode before servicing any interrupt requests. The GPIO interrupt allows the controller to wake-up periodically and poll system components while maintaining a very low average power consumption. To achieve the lowest possible current during suspend mode, all I/O should be held at VCC or Gnd. This also applies to internal port pins that may not be bonded in a particular package. Typical code for entering suspend is shown below: ... ... mov a, 09h iowr FFh nop ... ; All GPIO set to low-power state (no floating pins) ; Enable GPIO interrupts if desired for wake-up ; Set suspend and run bits ; Write to Status and Control Register - Enter suspend, wait for USB activity (or GPIO Interrupt) ; This executes before any ISR ; Remaining code for exiting suspend routine
9.0
General-Purpose I/O (GPIO) Ports
GPIO CFG OE
VCC
mode 2-bits Q1 Data Out Latch Control Q2
Internal Data Bus Port Write
14 k GPIO PIN Q3*
Port Read
Data In Latch Control
Reg_Bit STRB
(Latch is Transparent except in HAPI mode)
Data Interrupt Latch
Interrupt Enable Interrupt Controller
*Port 0,1,2: Low Isink Port 3: High Isink
Figure 9-1. Block Diagram of a GPIO Pin
There are up to 32 GPIO pins (P0[7:0], P1[7:0], P2[7:0], and P3[7:0]) for the hardware interface. The number of GPIO pins changes based on the package type of the chip. Each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. Port 3 offers a higher current drive, with typical current sink capability of 12 mA. The data for each GPIO port is accessible through the data registers. Port data registers are shown in Figure 9-2 through Figure 9-5, and are set to 1 on reset.
Document #: 38-08001 Rev. **
Page 17 of 48
CY7C64013 CY7C64113
7 P0[7] 6 P0[6] 5 P0[5] 4 P0[4] 3 P0[3] 2 P0[2] 1 P0[1] 0 P0[0]
Figure 9-2. Port 0 Data 0x00 (read/write) 7 P1[7] 6 P1[6] 5 P1[5] 4 P1[4] 3 P1[3] 2 P1[2] 1 P1[1] 0 P1[0]
Figure 9-3. Port 1 Data 0x01 (read/write) 7 P2[7] 6 P2[6] 5 P2[5] 4 P2[4] 3 P2[3] 2 P2[2] 1 P2[1] 0 P2[0]
Figure 9-4. Port 2 Data 0x02 (read/write) 7 P3[7] (see text) 6 P3[6] 5 P3[5] 4 P3[4] 3 P3[3] 2 P3[2] 1 P3[1] 0 P3[0]
Figure 9-5. Port 3 Data 0x03 (read/write) Special care should be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB Specifications. If a `1' is written to the unused data bit and the port is configured with open drain outputs, the unused data bit remains in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a `0.' Notice that the CY7C64013 part always requires that the data bits P1[7:3], P2[7,1,0], and P3[7:3] be written with a `0.' In normal non-HAPI mode, reads from a GPIO port always return the present state of the voltage at the pin, independent of the settings in the Port Data Registers. If HAPI mode is activated for a port, reads of that port return latched data as controlled by the HAPI signals (see Section 14.0). During reset, all of the GPIO pins are set to a high-impedance input state (`1' in open drain mode). Writing a `0' to a GPIO pin drives the pin LOW. In this state, a `0' is always read on that GPIO pin unless an external source overdrives the internal pull-down device.
9.1
GPIO Configuration Port
Every GPIO port can be programmed as inputs with internal pull-ups, open drain outputs, and traditional CMOS outputs. In addition, the interrupt polarity for each port can be programmed. With positive interrupt polarity, a rising edge (`0' to `1') on an input pin causes an interrupt. With negative polarity, a falling edge (`1' to `0') on an input pin causes an interrupt. As shown in the table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are disabled. The GPIO Configuration Port register provides two bits per port to program these features. The possible port configurations are detailed in Table 9-1: Table 9-1. Port Configurations Port Configuration bits 11 10 01 00 (Reset State) Pin Interrupt Bit 0 1 0 1 0 1 0 1 Driver Mode Resistive Resistive CMOS Output Open Drain Open Drain Open Drain Open Drain Open Drain Interrupt Polarity Disabled - Disabled Disabled Disabled - Disabled (Default Condition) +
In "Resistive" mode, a 14-k pull-up resistor is conditionally enabled for all pins of a GPIO port. An I/O pin is driven HIGH through a 14-k pull-up resistor when a `1' has been written to the pin. The output pin is driven LOW with the pull-up disabled when a `0' has been written to the pin. An I/O pin that has been written as a `1' can be used as an input pin with the integrated 14-k pull-up resistor. Resistive mode selects a negative (falling edge) interrupt polarity on all pins that have the GPIO interrupt enabled.
Document #: 38-08001 Rev. **
Page 18 of 48
CY7C64013 CY7C64113
In "CMOS" mode, all pins of the GPIO port are outputs that are actively driven. A CMOS port is not a possible source for interrupts. In "Open Drain" mode, the internal pull-up resistor and CMOS driver (HIGH) are both disabled. An open drain I/O pin that has been written as a `1' can be used as an input or an open drain output. An I/O pin that has been written as a `0' drives the output low. The interrupt polarity for an open drain GPIO port can be selected as positive (rising edge) or negative (falling edge). During reset, all of the bits in the GPIO Configuration Register are written with `0' to select Open Drain output for all GPIO ports as the default configuration. 7 Port 3 Config Bit 1 6 Port 3 Config Bit 0 5 Port 2 Config Bit 1 4 Port 2 Config Bit 0 3 Port 1 Config Bit 1 2 Port 1 Config Bit 0 1 Port 0 Config Bit 1 0 Port 0 Config Bit 0
Figure 9-6. GPIO Configuration Register 0x08 (read/write)
9.2
GPIO Interrupt Enable Ports
Each GPIO pin can be individually enabled or disabled as an interrupt source. The Port 0-3 Interrupt Enable registers provide this feature with an interrupt enable bit for each GPIO pin. When HAPI mode (discussed in Section 14.0) is enabled the GPIO interrupts are blocked, including ports not used by HAPI, so GPIO pins cannot be used as interrupt sources. During a reset, GPIO interrupts are disabled by clearing all of the GPIO interrupt enable ports. Writing a `1' to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin. All GPIO pins share a common interrupt, as discussed in Section 16.7. 7 P0[7] 6 P0[6] 5 P0[5] 4 P0[4] 3 P0[3] 2 P0[2] 1 P0[1] 0 P0[0]
Figure 9-7. Port 0 Interrupt Enable 0x04 (write only) 7 P1[7] 6 P1[6] 5 P1[5] 4 P1[4] 3 P1[3] 2 P1[2] 1 P1[1] 0 P1[0]
Figure 9-8. Port 1 Interrupt Enable 0x05 (write only) 7 P2[7] 6 P2[6] 5 P2[5] 4 P2[4] 3 P2[3] 2 P2[2] 1 P2[1] 0 P2[0]
Figure 9-9. Port 2 Interrupt Enable 0x06 (write only) 7 reserved set to zero 6 P3[6] 5 P3[5] 4 P3[4] 3 P3[3] 2 P3[2] 1 P3[1] 0 P3[0]
Figure 9-10. Port 3 Interrupt Enable 0x07 (write only)
Document #: 38-08001 Rev. **
Page 19 of 48
CY7C64013 CY7C64113
10.0 DAC Port
VCC
Internal Data Bus Data Out Latch Q1 Suspend (Bit 3 of Register 0xFF) 14 k DAC Write Isink Register Internal Buffer 4 bits Isink DAC
DAC I/O Pin
DAC Read Interrupt Enable Interrupt Polarity Interrupt Logic
to Interrupt Controller
Figure 10-1. Block Diagram of a DAC Pin The CY7C64113 features a Digital to Analog Conversion (DAC) port which has programmable current sink on each I/O pin. Writing a `1' to a DAC I/O pin disables the output current sink (Isink DAC) and drives the I/O pin HIGH through an integrated 14-k resistor. When a `0' is written to a DAC I/O pin, the Isink DAC is enabled and the pull-up resistor is disabled. This causes the Isink DAC to sink current to drive the output LOW. The amount of sink current for the DAC I/O pin is programmable over 16 values based on the contents of the DAC Isink Register for that output pin. DAC[1:0] are high-current outputs that are programmable from 3.2 mA to 16 mA (typical). DAC[7:2] are low-current outputs, programmable from 0.2 mA to 1.0 mA (typical). When the suspend bit in Processor Status and Control Register (0xFF) is set, the Isink DAC block of the DAC circuitry is disabled. Special care should be taken when the CY7C64x13 device is placed in the suspend mode. The DAC Port Data Register(0x30) should normally be loaded with all `1's (0xFF) before setting the suspend bit. If any of the DAC bits are set to `0' when the device is suspended, that DAC input will float. The floating pin could result in excessive current consumption by the device, unless an external load places the pin in a deterministic state. When a DAC I/O bit is written as a `1', the I/O pin is an output pulled HIGH through the 14-k resistor or an input with an internal 14-k pull-up resistor. All DAC port data bits are set to `1' during reset. Low current outputs 0.2 mA to 1.0 mA typical 7 DAC[7] 6 DAC[6] 5 DAC[5] 4 DAC[4] 3 DAC[3] 2 DAC[2] High current outputs 3.2 mA to 16 mA typical 1 DAC[1] 0 DAC[0]
Figure 10-2. DAC Port Data 0x30 (read/write)
10.1
DAC Isink Registers
Each DAC I/O pin has an associated DAC Isink register to program the output sink current when the output is driven LOW. The first Isink register (0x38) controls the current for DAC[0], the second (0x39) for DAC[1], and so on until the Isink register at 0x3F controls the current to DAC[7]. Writing all `0's to the Isink register causes 1/5 of the max. current to flow through the DAC I/O pin. Writing all `1's to the Isink register provides the maximum current flow through the pin. The other 14 states of the DAC sink current are evenly spaced between these two values. Isink Value 7 reserved 6 reserved 5 reserved 4 reserved 3 Isink[3] 2 Isink[2] 1 Isink[1] 0 Isink[0]
Figure 10-3. DAC Port Isink 0x38 to 0x3F (write only)
Document #: 38-08001 Rev. **
Page 20 of 48
CY7C64013 CY7C64113
10.2 DAC Port Interrupts
A DAC port interrupt can be enabled/disabled for each pin individually. The DAC Port Interrupt Enable register provides this feature with an interrupt enable bit for each DAC I/O pin. Writing a `1' to a bit in this register enables interrupts from the corresponding bit position. Writing a `0' to a bit in the DAC Port Interrupt Enable register disables interrupts from the corresponding bit position. All of the DAC Port Interrupt Enable register bits are cleared to `0' during a reset. All DAC pins share a common interrupt, as explained in Section 16.6. 7 DAC[7] 6 DAC[6] 5 DAC[5] 4 DAC[4] 3 DAC[3] 2 DAC[2] 1 DAC[1] 0 DAC[0]
Figure 10-4. DAC Port Interrupt Enable 0x31 (write only) As an additional benefit, the interrupt polarity for each DAC pin is programmable with the DAC Port Interrupt Polarity register. Writing a `0' to a bit selects negative polarity (falling edge) that causes an interrupt (if enabled) if a falling edge transition occurs on the corresponding input pin. Writing a `1' to a bit in this register selects positive polarity (rising edge) that causes an interrupt (if enabled) if a rising edge transition occurs on the corresponding input pin. All of the DAC Port Interrupt Polarity register bits are cleared during a reset. 7 DAC[7] 6 DAC[6] 5 DAC[5] 4 DAC[4] 3 DAC[3] 2 DAC[2] 1 DAC[1] 0 DAC[0]
Figure 10-5. DAC Port Interrupt Polarity 0x32 (write only)
11.0
12-Bit Free-Running Timer
The 12-bit timer provides two interrupts (128-s and 1.024-ms) and allows the firmware to directly time events that are up to 4 ms in duration. The lower 8 bits of the timer can be read directly by the firmware. Reading the lower 8 bits latches the upper 4 bits into a temporary register. When the firmware reads the upper 4 bits of the timer, it is accessing the count stored in the temporary register. The effect of this logic is to ensure a stable 12-bit timer value can be read, even when the two reads are separated in time.
11.1
7
Timer (LSB)
6 Timer Bit 6 5 Timer Bit 5 4 Timer Bit 4 3 Timer Bit 3 2 Timer Bit 2 1 Timer Bit 1 0 Timer Bit 0 Timer Bit 7
Figure 11-1. Timer Register 0x24 (read only)
11.2
7
Timer (MSB)
6 Reserved 5 Reserved 4 Reserved 3 Timer Bit 11 2 Timer Bit 10 1 Timer Bit 9 0 Timer Bit 8
Reserved
Figure 11-2. Timer Register 0x25 (read only)
Document #: 38-08001 Rev. **
Page 21 of 48
CY7C64013 CY7C64113
1.024-ms Interrupt 128-s Interrupt
11
10
9
8
7
6
5
4
3
2
1
0
1-MHz Clock
L3 D3
L2 D2
L1 D1
L0 D0 D7 D6 D5 D4 D3 D2 D1 D0 To Timer Register 8
Figure 11-3. Timer Block Diagram
12.0
I2C and HAPI Configuration Register
Internal hardware supports communication with external devices through two interfaces: a two-wire I2C compatible interface, and a HAPI for 1, 2, or 3 byte transfers. The I2C compatible interface and HAPI functions, discussed in detail in Sections 13.0 and 14.0, share a common configuration register (see Figure 12-1). All bits of this register are cleared on reset. 7 R/W I C Position
2
6
5 R/W
4 R/W DRDY Polarity
3 R Latch Empty
2 R Data Ready
1 R/W HAPI Port Width Bit 1
0 R/W HAPI Port Width Bit 0
Reserved
LEMPTY Polarity
Figure 12-1. HAPI/I2C Configuration Register 0x09 (read/write) Bits [7,1:0] of the HAPI/I2C Configuration Register control the pin out configuration of the HAPI and I2C compatible interfaces. Bits [5:2] are used in HAPI mode only, and are described in Section 14.0. Table 12-1 shows the HAPI port configurations, and Table 12-2 shows I2C pin location configuration options. These I2C compatible options exist due to pin limitations in certain packages, and to allow simultaneous HAPI and I2C compatible operation. HAPI operation is enabled whenever either HAPI Port Width Bit (Bit 1 or 0) is non-zero. This affects GPIO operation as described in Section 14.0. I2C compatible blocks must be separately enabled as described in Section 13.0. Table 12-1. HAPI Port Configuration Port Width Bits[1:0] 11 10 01 00 Table 12-2. I C Port Configuration I2C Position Bit[7] X 0 1 Document #: 38-08001 Rev. ** Port Width Bit[1] 1 0 0 I2C Position I2C on P2[1:0], 0:SCL, 1:SDA I2C on P1[1:0], 0:SCL, 1:SDA I2C on P2[1:0], 0:SCL, 1:SDA Page 22 of 48
2
HAPI Port Width 24 Bits: P3[7:0], P1[7:0], P0[7:0] 16 Bits: P1[7:0], P0[7:0] 8 Bits: P0[7:0] No HAPI Interface
CY7C64013 CY7C64113
13.0 I2C Compatible Controller
The I2C compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and multi-master modes of operation. The I2C compatible block functions by handling the low-level signaling in hardware, and issuing interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the hardware keeps the I2C compatible bus idle if necessary. The I2C compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in Section 16.8. The I2C compatible interface consists of two registers, an I2C Data Register (Figure 13-1) and an I2C Status and Control Register (Figure 13-2). The Data Register is implemented as separate read and write registers. Generally, the I2C Status and Control Register should only be monitored after the I2C interrupt, as all bits are valid at that time. Polling this register at other times could read misleading bit status if a transaction is underway. The I2C SCL clock is connected to bit 0 of GPIO port 1 or GPIO port 2, and the I2C SDA data is connected to bit 1 of GPIO port 1 or GPIO port 2. Refer to Section 12.0 for the bit definitions and functionality of the HAPI/I2C Configuration Register, which is used to set the locations of the configurable I2C compatible pins. Once the I2C compatible functionality is enabled by setting bit 0 of the I2C Status & Control Register, the two LSB bits ([1:0]) of the corresponding GPIO port are placed in Open Drain mode, regardless of the settings of the GPIO Configuration Register.The electrical characteristics of the I2C compatible interface is the same as that of GPIO ports 1 and 2. Note that the IOL (max) is 2 mA @ VOL = 2.0 V for ports 1 and 2. All control of the I2C clock and data lines is performed by the I2C compatible block. 7 I C Data 7
2 2
6 I C Data 6
2
5 I C Data 5
2 2
4 I C Data 4
2
3 I C Data 3
2
2 I C Data 2
2
1 I C Data 1
2
0 I C Data 0
Figure 13-1. I C Data Register 0x29 (separate read/write registers)
7 R/W MSTR Mode
6 R/W Continue/ Busy
5 R/W Xmit Mode
4 R/W ACK
3 R/W Addr
2 R/W ARB Lost/ Restart
1 R/W Received Stop
0 R/W I2C Enable
Figure 13-2. I2C Status and Control Register 0x28 (read/write) The I2C Status and Control register bits are defined in Table 13-1, with a more detailed description following. Table 13-1. I2C Status and Control Register Bit Definitions Bit 0 1 2 3 4 5 6
2
Name I C Enable Received Stop ARB Lost/Restart Addr ACK Xmit Mode Continue / Busy
2
Description Write to 1 to enable I C compatible function. When cleared, I2C compatible GPIO pins operate normally. Reads 1 only in slave receive mode, when I2C Stop bit detected (unless firmware did not ACK the last transaction). Reads 1 to indicate master has lost arbitration. Reads 0 otherwise. Write to 1 in master mode to perform a restart sequence (also set Continue bit). Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration. Reads 0 otherwise. This bit should always be written as 0. In receive mode, write 1 to generate ACK, 0 for no ACK. In transmit mode, reads 1 if ACK was received, 0 if no ACK received. Write to 1 for transmit mode, 0 for receive mode. Write 1 to indicate ready for next transaction. Reads 1 when I2C compatible block is busy with a transaction, 0 when transaction is complete. Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration. Clearing from 1 to 0 generates Stop bit.
7
MSTR Mode
Document #: 38-08001 Rev. **
Page 23 of 48
CY7C64013 CY7C64113
MSTR Mode: Setting this bit causes the I2C compatible block to initiate a master mode transaction by sending a start bit and transmitting the first data byte from the data register (this typically holds the target address and R/W bit). Subsequent bytes are initiated by setting the Continue bit, as described below. In master mode, the I2C compatible block generates the clock (SCK), and drives the data line as required depending on transmit or receive state. The I2C compatible block performs any required arbitration and clock synchronization. The loss of arbitration results in the clearing of this bit, the setting of the ARB Lost bit, and the generation of an interrupt to the microcontroller. If the chip is the target of an external master that wins arbitration, then the interrupt is held off until the transaction from the external master is completed. When MSTR Mode is cleared from 1 to 0 by a firmware write, an I2C Stop bit is generated. Continue / Busy: This bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin. In other words, the bit has responded to an interrupt request and has completed the required update or read of the data register. During a read this bit indicates if the hardware is busy and is locking out additional writes to the I2C Status and Control register. This locking allows the hardware to complete certain operations that may require an extended period of time. Following an I2C interrupt, the I2C compatible block does not return to the Busy state until firmware sets the Continue bit. This allows the firmware to make one control register write without the need to check the Busy bit. Xmit Mode: This bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. Clear this bit for receive mode. Firmware generally determines the value of this bit from the R/W bit associated with the I2C address packet. The Xmit Mode bit state is ignored when initially writing the MSTR Mode or the Restart bits, as these cases always cause transmit mode for the first byte. ACK: This bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ACK signal on the I2C compatible bus. Writing a 1 to this bit generates an ACK (SDA LOW) on the I2C compatible bus at the ACK bit time. During transmits (Xmit Mode=1), this bit should be cleared. Addr: This bit is set by the I2C compatible block during the first byte of a slave receive transaction, after an I2C start or restart. The Addr bit is cleared when the firmware sets the Continue bit. This bit allows the firmware to recognize when the master has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred. ARB Lost/Restart: This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along with the Continue and MSTR Mode bits) to perform an I2C restart sequence. The I2C target address for the restart must be written to the data register before setting the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware during the restart sequence. Receive Stop: This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive Stop bit is not set if the firmware terminates the I2C transaction by not acknowledging the previous byte transmitted on the I2C compatible bus, e.g., in receive mode if firmware sets the Continue bit and clears the ACK bit. I2C Enable: Set this bit to override GPIO definition with I2C compatible function on the two I2C compatible pins. When this bit is cleared, these pins are free to function as GPIOs. In I2C compatible mode, the two pins operate in open drain mode, independent of the GPIO configuration setting.
14.0
Hardware Assisted Parallel Interface (HAPI)
The CY7C64x13 processor provides a hardware assisted parallel interface for bus widths of 8, 16, or 24 bits, to accommodate data transfer with an external microcontroller or similar device. Control bits for selecting the byte width are in the HAPI/I2C Configuration Register (Figure 12-1), bits 1 and 0. Signals are provided on Port 2 to control the HAPI interface. Table 14-1 describes these signals and the HAPI control bits in the HAPI/I2C Configuration Register. Enabling HAPI causes the GPIO setting in the GPIO Configuration Register (0x08) to be overridden. The Port 2 output pins are in CMOS output mode and Port 2 input pins are in input mode (open drain mode with Q3 OFF in Figure 9-1).
Document #: 38-08001 Rev. **
Page 24 of 48
CY7C64013 CY7C64113
Table 14-1. Port 2 Pin and HAPI Configuration Bit Definitions Pin P2[2] P2[3] P2[4] P2[5] P2[6] Bit 2 3 4 Name LatEmptyPin DReadyPin STB OE CS Name Data Ready Latch Empty DRDY Polarity Direction Out Out In In In R/W R R R/W Description (Port 2 Pin) Ready for more input data from external interface. Output data ready for external interface. Strobe signal for latching incoming data. Output Enable, causes chip to output data. Chip Select (Gates STB and OE). Description (HAPI/I2C Configuration Register) Asserted after firmware writes data to Port 0, until OE driven LOW. Asserted after firmware reads data from Port 0, until STB driven LOW. Determines polarity of Data Ready bit and DReadyPin: If 0, Data Ready is active LOW, DReadyPin is active HIGH. If 1, Data Ready is active HIGH, DReadyPin is active LOW. Determines polarity of Latch Empty bit and LatEmptyPin: If 0, Latch Empty is active LOW, LatEmptyPin is active HIGH. If 1, Latch Empty is active HIGH, LatEmptyPin is active LOW.
5
LEMPTY Polarity
R/W
HAPI Read by External Device from CY7C64x13: In this case (see Figure 23-3), firmware writes data to the GPIO ports. If 16-bit or 24-bit transfers are being made, Port 0 should be written last, since writes to Port 0 asserts the Data Ready bit and the DReadyPin to signal the external device that data is available. The external device then drives the OE and CS pins active (LOW), which causes the HAPI data to be output on the port pins. When OE is returned HIGH (inactive), the HAPI/GPIO interrupt is generated. At that point, firmware can reload the HAPI latches for the next output, again writing Port 0 last. The Data Ready bit reads the opposite state from the external DReadyPin on pin P2[3]. If the DRDY Polarity bit is 0, DReadyPin is active HIGH, and the Data Ready bit is active LOW. HAPI Write by External Device to CY7C64x13: In this case (see Figure 23-4), the external device drives the STB and CS pins active (LOW) when it drives new data onto the port pins. When this happens, the internal latches become full which causes the Latch Empty bit to be deasserted. When STB is returned HIGH (inactive), the HAPI/GPIO interrupt is generated. Firmware then reads the parallel ports to empty the HAPI latches. If 16-bit or 24-bit transfers are being made, Port 0 should be read last because reads from Port 0 assert the Latch Empty bit and the LatEmptyPin to signal the external device for more data. The Latch Empty bit reads the opposite state from the external LatEmptyPin on pin P2[2]. If the LEMPTY Polarity bit is 0, LatEmptyPin is active HIGH, and the Latch Empty bit is active LOW.
15.0
7 R
Processor Status and Control Register
6 R/W Watch Dog Reset 5 R/W USB Bus Reset Interrupt 4 R/W Power-On Reset 3 R/W Suspend 2 R Interrupt Enable Sense reserved 1 0 R/W Run
IRQ Pending
Figure 15-1. Processor Status and Control Register 0xFF The Run bit, bit 0, is manipulated by the HALT instruction. When Halt is executed, all the bits of the Processor Status and Control Register are cleared to 0. Since the run bit is cleared, the processor stops at the end of the current instruction. The processor remains halted until an appropriate reset occurs (power-on or watch dog). This bit should normally be written as a `1.' Bit 1 is reserved and must be written as a zero. The Interrupt Enable Sense (bit 2) shows whether interrupts are enabled or disabled. Firmware has no direct control over this bit as writing a zero or one to this bit position has no effect on interrupts. A `0' indicates that interrupts are masked off and a `1' indicates that the interrupts are enabled. This bit is further gated with the bit settings of the Global Interrupt Enable Register (0x20) and USB End Point Interrupt Enable Register (0x21). Instructions DI, EI, and RETI manipulate the state of this bit. Writing a `1' to the Suspend bit (bit 3) halts the processor and causes the microcontroller to enter the suspend mode that significantly reduces power consumption. A pending, enabled interrupt or USB bus activity causes the device to come out of suspend. After coming out of suspend, the device resumes firmware execution at the instruction following the IOWR which put the part into suspend. An IOWR attempting to put the part into suspend is ignored if non-idle USB bus activity is present. See Section 8.0 for more details on suspend mode operation. Document #: 38-08001 Rev. ** Page 25 of 48
CY7C64013 CY7C64113
The Power-On Reset (bit 4) is set to `1' during a power-on reset. The firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a power-on condition or a watch dog timeout. Note that a POR event may be followed by a watch dog reset before firmware begins executing, as explained below. The USB Bus Reset Interrupt (bit 5) occurs when a USB Bus Reset is received on the upstream port. The USB Bus Reset is a single-ended zero (SE0) that lasts from 12 to 16 s. An SE0 is defined as the condition in which both the D+ line and the D- line are LOW at the same time. When the SIE detects that this SE0 condition is removed, the USB Bus Reset interrupt bit is set in the Processor Status and Control Register and a USB Bus Reset interrupt is generated. The Watch Dog Reset (bit 6) is set during a reset initiated by the Watch Dog Timer. This indicates the Watch Dog Timer went for more than tWATCH (8 ms minimum) between Watch Dog clears. This can occur with a POR event, as noted below. The IRQ pending (bit 7), when set, indicates that one or more of the interrupts has been recognized as active. An interrupt remains pending until its interrupt enable bit is set (registers 0x20 or 0x21) and interrupts are globally enabled. At that point, the internal interrupt handling sequence clears this bit until another interrupt is detected as pending. During power-up, the Processor Status and Control Register is set to 00010001, which indicates a POR (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). During the 96 ms suspend at start-up (explained in Section 7.1), a Watch Dog Reset also occurs unless this suspend is aborted by an upstream SE0 before 8 ms. If a WDR occurs during the power-up suspend interval, firmware reads 01010001 from the Status and Control Register after power-up. Normally, the POR bit should be cleared so a subsequent WDR can be clearly identified. If an upstream bus reset is received before firmware examines this register, the Bus Reset bit may also be set. During a Watch Dog Reset, the Processor Status and Control Register is set to 01XX0001, which indicates a Watch Dog Reset (bit 6 set) has occurred and no interrupts are pending (bit 7 clear). The Watch Dog Reset does not effect the state of the POR and the Bus Reset Interrupt bits.
16.0
Interrupts
Interrupts are generated by the GPIO/DAC pins, the internal timers, I2C compatible interface or HAPI operation, or on various USB traffic conditions. All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a `1' to a bit position enables the interrupt associated with that bit position. During a reset, the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared, effectively disabling all interrupts. 7 Reserved 6 R/W IC Interrupt Enable
2
5 R/W GPIO/HAPI Interrupt Enable
4 R/W DAC Interrupt Enable
3 Reserved
2 R/W 1.024-ms Interrupt Enable
1 R/W 128-s Interrupt Enable
0 R/W USB Bus RST Interrupt Enable
Figure 16-1. Global Interrupt Enable Register 0x20 (read/write) 7 Reserved 6 Reserved 5 Reserved 4 R/W EPB1 Interrupt Enable 3 R/W EPB0 Interrupt Enable 2 R/W EPA2 Interrupt Enable 1 R/W EPA1 Interrupt Enable 0 R/W EPA0 Interrupt Enable
Figure 16-2. USB Endpoint Interrupt Enable Register 0x21 (read/write) The interrupt controller contains a separate flip-flop for each interrupt. See Figure 16-3 for the logic block diagram of the interrupt controller. When an interrupt is generated, it is first registered as a pending interrupt. It stays pending until it is serviced or a reset occurs. A pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enable registers. The highest priority interrupt request is serviced following the completion of the currently executing instruction. When servicing an interrupt, the hardware first disables all interrupts by clearing the Global Interrupt Enable bit in the CPU (the state of this bit can be read at Bit 2 of the Processor Status and Control Register). Second, the flip-flop of the current interrupt is cleared. This is followed by an automatic CALL instruction to the ROM address associated with the interrupt being serviced (i.e., the Interrupt Vector, see Section 16.1). The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service routine by executing an EI instruction. Interrupts can be nested to a level limited only by the available stack space. The Program Counter value, as well as the Carry and Zero flags (CF, ZF), are stored onto the Program Stack by the automatic CALL instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for ensuring that the processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first command in the ISR to save the accumulator value and the POP A instruction should be used to restore the accumulator value
Document #: 38-08001 Rev. **
Page 26 of 48
CY7C64013 CY7C64113
just before the RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI instruction is executed. The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the RETI that exists the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).
16.1
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed in Table 16-1. The lowest-numbered interrupt (USB Bus Reset interrupt) has the highest priority, and the highest-numbered interrupt (I2C interrupt) has the lowest priority. Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h--which corresponds to the first entry in the Interrupt Vector Table. Because the JMP instruction is 2 bytes long, the interrupt vectors occupy 2 bytes.
USB Reset Clear CLR 1 USB Reset Int D CLK Q Enable [0] (Reg 0x20) USB Reset IRQ 128-s CLR 128-s IRQ 1-ms CLR 1-ms IRQ AddA EP0 CLR AddA EP0 IRQ AddA EP1 CLR AddA EP1 IRQ AddA EP2 CLR AddA EP2 IRQ AddA EP3 CLR AddA EP3 IRQ AddA EP4 CLR AddA EP4 IRQ
Interrupt Vector
To CPU
CPU
IRQout
IRQ Sense IRQ
CLR 1 AddA ENP2 Int D CLK Q Enable [2] (Reg 0x21)
Global Interrupt Enable Bit CLR
Int Enable Sense
Controlled by DI, EI, and RETI Instructions
DAC CLR DAC IRQ GPIO CLR GPIO IRQ I2C CLR CLR 1 I2C Int D CLK Q Enable [6] (Reg 0x20) I2C IRQ Interrupt Priority Encoder
Interrupt Acknowledge
Figure 16-3. Interrupt Controller Functional Diagram
Document #: 38-08001 Rev. **
Page 27 of 48
CY7C64013 CY7C64113
Table 16-1. Interrupt Vector Assignments Interrupt Vector Number Not Applicable 1 2 3 4 5 6 7 8 9 10 11 12 ROM Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 Function Execution after Reset begins here USB Bus Reset interrupt 128-s timer interrupt 1.024-ms timer interrupt USB Address A Endpoint 0 interrupt USB Address A Endpoint 1 interrupt USB Address A Endpoint 2 interrupt USB Address A Endpoint 3 interrupt USB Address A Endpoint 4 interrupt Reserved DAC interrupt GPIO / HAPI interrupt I2C interrupt
A pending address can be read from the Interrupt Vector Register (Figure 16-4). The value read from this register is only valid if the Global Interrupt bit has been disabled, by executing the DI instruction or in an Interrupt Service Routine before interrupts have been re-enabled. The value read from this register is the interrupt vector address; for example, a 0x06 indicates the 1 ms timer interrupt is the highest priority pending interrupt. 7 Reserved 6 Reserved 5 Reserved 4 R Interrupt Vector Bit 4 3 R Interrupt Vector Bit 3 2 R Interrupt Vector Bit 2 1 R Interrupt Vector Bit 1 0 R Reads `0'
Figure 16-4. Interrupt Vector Register 0x23 (read only)
16.2
Interrupt Latency
(Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) + (5 clock cycles for the JMP instruction)
Interrupt latency can be calculated from the following equation: Interrupt latency =
For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the Interrupt Service Routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is issued. For a 12-MHz internal clock (6-MHz crystal), 20 clock periods is 20 / 12 MHz = 1.667 s.
16.3
USB Bus Reset Interrupt
The USB Controller recognizes a USB Reset when a Single Ended Zero (SE0) condition persists on the upstream USB port for 12-16 s (the Reset may be recognized for an SE0 as short as 12 s, but is always recognized for an SE0 longer than 16 s). SE0 is defined as the condition in which both the D+ line and the D- line are LOW. Bit 5 of the Status and Control Register is set to record this event. The interrupt is asserted at the end of the Bus Reset. If the USB reset occurs during the start-up delay following a POR, the delay is aborted as described in Section 7.1. The USB Bus Reset Interrupt is generated when the SE0 state is deasserted. A USB Bus Reset clears the following registers: SIE Section:USB Device Address Registers (0x10, 0x40)
Document #: 38-08001 Rev. **
Page 28 of 48
CY7C64013 CY7C64113
16.4 Timer Interrupt
There are two periodic timer interrupts: the 128-s interrupt and the 1.024-ms interrupt. The user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the suspend request first.
16.5
USB Endpoint Interrupts
There are five USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to a USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrupt is generated on the last packet of the transaction (e.g., on the host's ACK during an IN, or on the device ACK during on OUT). If no ACK is received during an IN transaction, no interrupt is generated.
16.6
DAC Interrupt
Each DAC I/O pin can generate an interrupt, if enabled. The interrupt polarity for each DAC I/O pin is programmable. A positive polarity is a rising edge input while a negative polarity is a falling edge input. All of the DAC pins share a single interrupt vector, which means the firmware needs to read the DAC port to determine which pin or pins caused an interrupt. If one DAC pin has triggered an interrupt, no other DAC pins can cause a DAC interrupt until that pin has returned to its inactive (non-trigger) state or the corresponding interrupt enable bit is cleared. The USB Controller does not assign interrupt priority to different DAC pins and the DAC Interrupt Enable Register is not cleared during the interrupt acknowledge process.
16.7
GPIO/HAPI Interrupt
Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware needs to read the GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. A block diagram of the GPIO interrupt logic is shown in Figure 16-5. Refer to Sections 9.1 and 9.2 for more information of setting GPIO interrupt polarity and enabling individual GPIO interrupts. If one port pin has triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process.
Port Configuration Register
OR Gate (1 input per GPIO pin)
GPIO Interrupt Flip Flop 1 D Q Interrupt Priority Encoder IRQout Interrupt Vector
GPIO Pin
M U X
CLR
1 = Enable 0 = Disable IRA
Port Interrupt Enable Register
1 = Enable 0 = Disable
Global GPIO Interrupt Enable (Bit 5, Register 0x20)
Figure 16-5. GPIO Interrupt Structure When HAPI is enabled, the HAPI logic takes over the interrupt vector and blocks any interrupt from the GPIO bits, including ports/bits not being used by HAPI. Operation of the HAPI interrupt is independent of the GPIO specific bit interrupt enables, and is enabled or disabled only by bit 5 of the Global Interrupt Enable Register (0x20) when HAPI is enabled. The settings of the GPIO bit interrupt enables on ports/bits not used by HAPI still effect the CMOS mode operation of those ports/bits. The effect of
Document #: 38-08001 Rev. **
Page 29 of 48
CY7C64013 CY7C64113
modifying the interrupt bits while the Port Config bits are set to "10" is shown in Table 9-1. The events that generate HAPI interrupts are described in Section 14.0.
16.8
I2C Interrupt
The I2C interrupt occurs after various events on the I2C compatible bus to signal the need for firmware interaction. This generally involves reading the I2C Status and Control Register (Figure 13-2) to determine the cause of the interrupt, loading/reading the I2C Data Register as appropriate, and finally writing the Status and Control Register to initiate the subsequent transaction. The interrupt indicates that status bits are stable and it is safe to read and write the I2C registers. Refer to Section 13.0 for details on the I2C registers. When enabled, the I2C compatible state machines generate interrupts on completion of the following conditions. The referenced bits are in the I2C Status and Control Register. 1. In slave receive mode, after the slave receives a byte of data. The Addr bit is set if this is the first byte since a start or restart signal was sent by the external master. Firmware must read or write the data register as necessary, then set the ACK, Xmit Mode, and Continue bits appropriately for the next byte. 2. In slave receive mode, after a stop bit is detected. The Received Stop bit is set. If the stop bit follows a slave receive transaction where the ACK bit was cleared to 0, no stop bit detection occurs. 3. In slave transmit mode, after the slave transmits a byte of data. The ACK bit indicates if the master that requested the byte acknowledged the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then sets the Xmit Mode and Continue bits as required. 4. In master transmit mode, after the master sends a byte of data. Firmware should load the Data Register if necessary, and set the Xmit Mode, MSTR Mode, and Continue/Busy bits appropriately. Clearing the MSTR Mode bit issues a stop signal to the I2C compatible bus and return to the idle state. 5. In master receive mode, after the master receives a byte of data. Firmware should read the data and set the Ack and Continue/Busy bits appropriately for the next byte. Clearing the Master bit at the same time causes the master state machine to issue a stop signal to the I2C compatible bus and leave the I2C compatible hardware in the idle state. 6. When the master loses arbitration. This condition clears the Master bit and sets the Arbitration Lost bit immediately and then waits for a stop signal on the I2C compatible bus to generate the interrupt. The Continue/Busy bit is cleared by hardware prior to interrupt conditions 1 to 4. Once the Data Register has been read or written, firmware should configure the other control bits and set the Continue bit for subsequent transactions. Following an interrupt from master mode, firmware should perform only one write to the Status and Control Register that sets the Continue bit, without checking the value of the Busy bit. The Busy bit may otherwise be active and I2C register contents may be changed by the hardware during the transaction, until the I2C interrupt occurs.
17.0
USB Overview
The USB hardware consists of the logic for a full-speed USB Port. The full-speed serial interface engine (SIE) interfaces the microcontroller to the USB bus. An external series resistor (Rext) must be placed in series with the D+ and D- lines, as close to the corresponding pins as possible, to meet the USB driver requirements of the USB specifications.
17.1
USB Serial Interface Engine (SIE)
The SIE allows the CY7C64x13 microcontroller to communicate with the USB host. The SIE simplifies the interface between the microcontroller and USB by incorporating hardware that handles the following USB bus activity independently of the microcontroller: * Bit stuffing/unstuffing * Checksum generation/checking * ACK/NAK/STALL * Token type identification * Address checking Firmware is required to handle the following USB interface tasks: * Coordinate enumeration by responding to SETUP packets * Fill and empty the FIFOs * Suspend/Resume coordination * Verify and select DATA toggle values
Document #: 38-08001 Rev. **
Page 30 of 48
CY7C64013 CY7C64113
17.2 USB Enumeration
The USB device is enumerated under firmware control. The following is a brief summary of the typical enumeration process of the CY7C64x13 by the USB host. For a detailed description of the enumeration process, refer to the USB specification. In this description, `Firmware' refers to embedded firmware in the CY7C64x13 controller. 1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor. 2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables. 3. The host computer performs a control read sequence and Firmware responds by sending the Device descriptor over the USB bus, via the on-chip FIFOs. 4. After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB address to the device. 5. Firmware stores the new address in its USB Device Address Register after the no-data control sequence completes. 6. The host sends a request for the Device descriptor using the new USB address. 7. Firmware decodes the request and retrieves the Device descriptor from program memory tables. 8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB bus. 9. The host generates control reads from the device to request the Configuration and Report descriptors. 10.Once the device receives a Set Configuration request, its functions may now be used.
17.3
USB Upstream Port Status and Control
USB status and control is regulated by the USB Status and Control Register, as shown in Figure 17-1. All bits in the register are cleared during reset. 7 R/W Endpoint Size 6 R/W Endpoint Mode 5 R D+ Upstream 4 R D- Upstream 3 R/C Bus Activity 2 R/W Control Bit 2 1 R/W Control Bit 1 0 R/W Control Bit 0
Figure 17-1. USB Status and Control Register 0x1F (read/write) The three control bits allow the upstream port to be driven manually by firmware. For normal USB operation, all of these bits must be cleared. Table 17-1 shows how the control bits affect the upstream port. Table 17-1. Control Bit Definition for Upstream Port Control Bits Control Action 000 001 010 011 100 101 110 111 Not Forcing (SIE Controls Driver) Force D+[0] HIGH, D-[0] LOW Force D+[0] LOW, D-[0] HIGH Force SE0; D+[0] LOW, D-[0] LOW Force D+[0] LOW, D-[0] LOW Force D+[0] HiZ, D-[0] LOW Force D+[0] LOW, D-[0] HiZ Force D+[0] HiZ, D-[0] HiZ
Bus Activity (bit 3) is a "sticky" bit that indicates if any non-idle USB event has occurred on the upstream USB port. Firmware should check and clear this bit periodically to detect any loss of bus activity. Writing a `0' to the Bus Activity bit clears it, while writing a `1' preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it. The Upstream D- and D+ (bits 4 and 5) are read only. These give the state of each upstream port pin individually: 1=HIGH, 0=LOW. Endpoint Mode (bit 6) and Endpoint Size (bit 7) are used to configure the number and size of USB endpoints. See Section 18.2 for a detailed description of these bits.
Document #: 38-08001 Rev. **
Page 31 of 48
CY7C64013 CY7C64113
18.0 USB Serial Interface Engine Operation
USB Device Address A includes up to five endpoints: EPA0, EPA1, EPA2, EPA3, and EPA4. Endpoint (EPA0) allows the USB host to recognize, set-up, and control the device. In particular, EPA0 is used to receive and transmit control (including set-up) packets.
18.1
USB Device Address
The USB Controller provides one USB Device Address with five endpoints. The USB Device Address Register contents are cleared during a reset, setting the USB device address to zero and marking this address as disabled. Figure 18-1 shows the format of the USB Address Registers. 7 Device Address Enable 6 Device Address Bit 6 5 Device Address Bit 5 4 Device Address Bit 4 3 Device Address Bit 3 2 Device Address Bit 2 1 Device Address Bit 1 0 Device Address Bit 0
Figure 18-1. USB Device Address Register 0x10 (read/write) Bit 7 (Device Address Enable) in the USB Device Address Register must be set by firmware before the SIE can respond to USB traffic to this address. The Device Addresses in bits [6:0] are set by firmware during the USB enumeration process to the non-zero address assigned by the USB host.
18.2
USB Device Endpoints
The CY7C64x13 controller supports one USB device address and five endpoints for communication with the host. The configuration of these endpoints, and associated FIFOs, is controlled by bits [7,6] of the USB Status and Control Register (0x1F). Bit 7 controls the size of the endpoints and bit 6 controls the number of endpoints. These configuration options are detailed in Table 18-1. The "unused" FIFO areas in the following table can be used by the firmware as additional user RAM space. Table 18-1. Memory Allocation for Endpoints [0,0] I/O status [7,6] Label
unused unused
[1,0] Size 8 8 8 8 8 Label
unused unused
[0,1] Size 8 8 8 32 32 Label EPA4 EPA3 EPA2 EPA1 EPA0 Start Address 0xD8 0xE0 0xE8 0xF0 0xF8 Size 8 8 8 8 8 Label EPA4 EPA3 EPA0 EPA1 EPA2
[1,1] Start Address 0xB0 0xA8 0xB8 0xC0 0xE0 Size 8 8 8 32 32
Start Address 0xD8 0xE0 0xE8 0xF0 0xF8
Start Address 0xA8 0xB0 0xB8 0xC0 0xE0
EPA2 EPA1 EPA0
EPA0 EPA1 EPA2
When the SIE writes data to a FIFO, the internal data bus is driven by the SIE; not the CPU. This causes a short delay in the CPU operation. The delay is three clock cycles per byte. For example, an 8-byte data write by the SIE to the FIFO generates a delay of 2 s (3 cycles/byte * 83.33 ns/cycle * 8 bytes).
18.3
USB Control Endpoint Mode Register
All USB devices are required to have a Control Endpoint 0 (EPA0) that is used to initialize and control each USB address. Endpoint 0 provides access to the device configuration information and allows generic USB status and control accesses. Endpoint 0 is bidirectional to both receive and transmit data. The other endpoints are unidirectional, but selectable by the user as IN or OUT endpoints. The endpoint mode register is cleared during reset. The endpoint zero EPA0 mode register uses the format shown in Figure 18-2. 7 Endpoint 0 SETUP Received 6 Endpoint 0 IN Received 5 Endpoint 0 OUT Received 4 ACK 3 Mode Bit 3 2 Mode Bit 2 1 Mode Bit 1 0 Mode Bit 0
Figure 18-2. USB Device Endpoint Zero Mode Register 0x12 (read/write)
Document #: 38-08001 Rev. **
Page 32 of 48
CY7C64013 CY7C64113
Bits[7:5] in the endpoint 0 mode registers are status bits that are set by the SIE to report the type of token that was most recently received by the corresponding device address. These bits must be cleared by firmware as part of the USB processing. The ACK bit (bit 4) is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. The SETUP PID status (bit 7) is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval, and subsequently, until the CPU first does an IORD to this endpoint 0 mode register. Bits[6:0] of the endpoint 0 mode register are locked from CPU write operations whenever the SIE has updated one of these bits, which the SIE does only at the end of the token phase of a transaction (SETUP... Data... ACK, OUT... Data... ACK, or IN... Data... ACK). The CPU can unlock these bits by doing a subsequent read of this register. Only endpoint 0 mode registers are locked when updated. The locking mechanism does not apply to the mode registers of other endpoints. Because of these hardware locking features, firmware must perform an IORD after an IOWR to an endpoint 0 register. This verifies that the contents have changed as desired, and that the SIE has not updated these values. While the SETUP bit is set, the CPU cannot write to the endpoint zero FIFOs. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. Refer to Table 18-1 for the appropriate endpoint zero memory locations. The Mode bits (bits [3:0]) control how the endpoint responds to USB bus traffic. The mode bit encoding is shown inTable 19-1. Additional information on the mode bits can be found inTable 19-2 and Table 19-3. Note that the SIE offers an "Ack out - Status in" mode and not an "Ack out - Nak in" mode. Therefore, if following the status stage of a Control Write transfer a USB host were to immediately start the next transfer, the new Setup packet could override the data payload of the data stage of the previous Control Write.
18.4
USB Non-Control Endpoint Mode Registers
The format of the non-control endpoint mode register is shown in Figure 18-3. 7 STALL 6 Reserved 5 Reserved 4 ACK 3 Mode Bit 3 2 Mode Bit 2 1 Mode Bit 1 0 Mode Bit 0
Figure 18-3. USB Non-Control Device Endpoint Mode Registers 0x14, 0x16, 0x42, 0x44, (read/write) The mode bits (bits [3:0]) of the Endpoint Mode Register control how the endpoint responds to USB bus traffic. The mode bit encoding is shown in Table 19-1. The ACK bit (bit 4) is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. If STALL (bit 7) is set, the SIE stalls an OUT packet if the mode bits are set to ACK-IN, and the SIE stalls an IN packet if the mode bits are set to ACK-OUT. For all other modes, the STALL bit must be a LOW. Bits 5 and 6 are reserved and must be written to zero during register writes.
18.5
USB Endpoint Counter Registers
There are five Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers contain byte count information for USB transactions, as well as bits for data packet status. The format of these registers is shown in Figure 18-4: 7 Data 0/1 Toggle 6 Data Valid 5 Byte Count Bit 5 4 Byte Count Bit 4 3 Byte Count Bit 3 2 Byte Count Bit 2 1 Byte Count Bit 1 0 Byte Count Bit 0
Figure 18-4. USB Endpoint Counter Registers 0x11, 0x13, 0x15, 0x41, 0x43 (read/write) The counter bits (bits [5:0]) indicate the number of data bytes in a transaction. For IN transactions, firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 32, inclusive. For OUT or SETUP transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the CRC bytes. Valid values are 2 to 34, inclusive. Data Valid bit 6 is used for OUT and SETUP tokens only. Data is loaded into the FIFOs during the transaction, and then the Data Valid bit is set if a proper CRC is received. If the CRC is not correct, the endpoint interrupt occurs, but Data Valid is cleared to a zero. Data 0/1 Toggle bit 7 selects the DATA packet's toggle state: 0 for DATA0, 1 for DATA1. For IN transactions, firmware must set this bit to the desired state. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit. Document #: 38-08001 Rev. ** Page 33 of 48
CY7C64013 CY7C64113
Whenever the count updates from a SETUP or OUT transaction on endpoint 0, the counter register locks and cannot be written by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on incoming SETUP or OUT transactions before firmware has a chance to read the data. Only endpoint 0 counter register is locked when updated. The locking mechanism does not apply to the count registers of other endpoints.
18.6
Endpoint Mode/Count Registers Update and Locking Mechanism
The contents of the endpoint mode and counter registers are updated, based on the packet flow diagram in Figure 18-5. Two time points, UPDATE and SETUP, are shown in the same figure. The following activities occur at each time point: UPDATE: 1. Endpoint Mode Register - All the bits are updated (except the SETUP bit of the endpoint 0 mode register). 2. Counter Registers - All bits are updated. 3. Interrupt - If an interrupt is to be generated as a result of the transaction, the interrupt flag for the corresponding endpoint is set at this time. For details on what conditions are required to generate an endpoint interrupt, refer to Table 19-2. 4. The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode register which was locked earlier. SETUP: The SETUP bit of the endpoint 0 mode register is forced HIGH at this time. This bit is forced HIGH by the SIE until the end of the data phase of a control write transfer. The SETUP bit can not be cleared by firmware during this time. The affected mode and counter registers of endpoint 0 are locked from any CPU writes once they are updated. These registers can be unlocked by a CPU read, only if the read operation occurs after the UPDATE. The firmware needs to perform a register read as a part of the endpoint ISR processing to unlock the effected registers. The locking mechanism on mode and counter registers ensures that the firmware recognizes the changes that the SIE might have made since the previous IO read of that register.
Document #: 38-08001 Rev. **
Page 34 of 48
CY7C64013 CY7C64113
1. IN Token
a) S Y N C I N A D D R E N D P C R C 5 S Y N C D A T A 1 C R C 1 6 S Y N C
data
A C K
Token Packet
Data Packet
H/S Pkt
update
b) S Y N C I N A D D R E N D P C R C 5 S Y N C NAK/ STALL H/S Pkt
update
H O S T
Token Packet
2. OUT or SETUP Token without CRC error
SOA U Y D T N D C Set R up E N D P C R C 5 S Y N C D A T A 1 C R C 1 6
update
data
S Y N C
ACK, NAK, STALL H/S Pkt
D E V I C E
Token Packet
Setup
Data Packet
3. OUT or SETUP Token with CRC error
O S A U Y D NTD C Set R up E N D P C R C 5 S Y N C D A T A 1 C R C 1 6
data
Token Packet
Data Packet
update only if FIFO update only if FIFO isis Written (see Table Written (see Table 19-3) 20-3)
Figure 18-5. Token/Data Packet Flow Diagram
Document #: 38-08001 Rev. **
Page 35 of 48
CY7C64013 CY7C64113
19.0 USB Mode Tables
Mode Disable Nak In/Out Status Out Only Stall In/Out Ignore In/Out Isochronous Out Status In Only Isochronous In Nak Out Ack Out(STALL[3]=0) Ack Out(STALL[3]=1) Nak Out - Status In Ack Out - Status In Nak In Ack IN(STALL[3]=0) Ack IN(STALL[3]=1) Nak In - Status Out Ack In - Status Out Encoding 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1001 1010 1011 1100 1101 1101 1110 1111 Setup ignore accept accept accept accept ignore accept ignore ignore ignore ignore accept accept ignore ignore ignore accept accept In ignore NAK stall stall ignore ignore TX 0 TX cnt ignore ignore ignore TX 0 TX 0 NAK TX cnt stall NAK TX cnt Out ignore NAK check stall ignore always stall ignore NAK ACK stall NAK ACK ignore ignore ignore check check Comments Ignore all USB traffic to this endpoint Forced from Set-up on Control endpoint, from modes other than 0000 For Control endpoints For Control endpoints For Control endpoints For Isochronous endpoints For Control Endpoints For Isochronous endpoints An ACK from mode 1001 --> 1000 This mode is changed by SIE on issuance of ACK --> 1000 An ACK from mode 1011 --> 1010 This mode is changed by SIE on issuance of ACK --> 1010 An ACK from mode 1101 --> 1100 This mode is changed by SIE on issuance of ACK --> 1100 An ACK from mode 1111 --> 111 Ack In - Status Out This mode is changed by SIE on issuance of ACK -->1110
Table 19-1. USB Register Mode Encoding
The `In' column represents the SIE's response to the token type. A disabled endpoint remains disabled until it is changed by firmware, and all endpoints reset to the disabled state. Any SETUP packet to an enabled endpoint with mode set to accept SETUPs is changed by the SIE to 0001 (NAKing). Any mode set to accept a SETUP, ACKs a valid SETUP transaction. Most modes that control transactions involving an ending ACK, are changed by the SIE to a corresponding mode which NAKs subsequent packets following the ACK. Exceptions are modes 1010 and 1110. A Control endpoint has three extra status bits for PID (Setup, In and Out), but must be placed in the correct mode to function as such. Non-Control endpoints should not be placed into modes that accept SETUPs. A `check' on an Out token during a Status transaction checks to see that the Out is of zero length and has a Data Toggle (DTOG) of `1'. If the DTOG bit is set and the received Out Packet has zero length, the Out is ACKed to complete the transaction. Otherwise, the Out is STALLed.
Note: 3. STALL bit is bit 7 of the USB Non-Control Device Endpoint Mode registers. For more information, refer to Section 18.4.
Document #: 38-08001 Rev. **
Page 36 of 48
CY7C64013 CY7C64113
Table 19-2. Decode table for Table 19-3: "Details of Modes for Differing Traffic Conditions" Properties of incoming packet Encoding Status bits What the SIE does to Mode bits PID Status bits
End Point Mode 3 2 1 0 Token Setup In Out The validity of the received data The quality status of the DMA buffer The number of received bytes Acknowledge phase completed count buffer dval DTOG DVAL COUNT Setup In Out ACK End Point Mode 3 2 1 0 Response Int
Interrupt?
Legend:
UC: unchanged x: don't care
TX: transmit RX: receive
TX0: transmit 0-length packet
available for Control endpoint only
The response of the SIE can be summarized as follows: 1. The SIE only responds to valid transactions and ignores non-valid ones. 2. The SIE generates an interrupt when a valid transaction is completed or when the FIFO is corrupted. FIFO corruption occurs during an OUT or SETUP transaction to a valid internal address that ends with a non-valid CRC. 3. An incoming Data packet is valid if the count is < Endpoint Size + 2 (includes CRC) and passes all error checking. 4. An IN is ignored by an OUT configured endpoint and vice versa. 5. The IN and OUT PID status is updated at the end of a transaction. 6. The SETUP PID status is updated at the beginning of the Data packet phase. 7. The entire Endpoint 0 mode register and the count register are locked from CPU writes at the end of any transaction to that endpoint in which either an ACK is transferred or the mode bits have changed. These registers are only unlocked by a CPU read of these registers, and only if that read happens after the transaction completes. This represents about a 1-s window in which the CPU is locked from register writes to these USB registers. Normally, the firmware should perform a register read at the beginning of the Endpoint ISRs to unlock and get the mode register information. The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction.
Document #: 38-08001 Rev. **
Page 37 of 48
CY7C64013 CY7C64113
Table 19-3. Details of Modes for Differing Traffic Conditions (see Table 19-2 for the decode legend) End Point Mode
3 2 1 0 token count buffer dval DTOG DVAL COUNT PID Setup In Out ACK
Set End Point Mode
3 2 1 0 response int
Setup Packet (if accepting)
See Table 19-1 See Table 19-1 See Table 19-1 Disabled 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x Out In Out In Out In x x x x x x x UC UC UC UC UC UC UC x x x x x x x UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 UC UC UC 1 UC 1 UC UC UC 1 UC UC UC UC UC UC UC UC NoChange NoChange NoChange NoChange NoChange NoChange NoChange ignore NAK NAK ignore ignore Stall Stall no yes yes no no yes yes Nak In/Out Setup Setup Setup <= 10 > 10 x data junk junk valid x invalid updates updates updates 1 updates 0 updates updates updates 1 1 1 UC UC UC UC UC UC 1 UC UC 0 0 0 1 ACK ignore ignore yes yes yes NoChange NoChange
Ignore In/Out
Stall In/Out
Control Write
Normal Out/premature status In 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Out Out Out In Out Out Out In Out Out Out In <= 10 > 10 x x <= 10 > 10 x x <= 10 > 10 x x data junk junk UC UC UC UC UC UC UC UC UC valid x invalid x valid x invalid x valid x invalid x updates updates updates UC UC UC UC UC UC UC UC UC 1 updates 0 UC UC UC UC UC UC UC UC UC updates updates updates UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 UC UC UC 1 UC UC UC 1 1 1 1 UC 1 UC UC UC 1 UC UC UC 1 UC UC 1 UC UC UC 1 UC UC UC 1 1 0 1 0 ACK ignore ignore TX 0 NAK ignore ignore TX 0 yes yes yes yes yes no no yes yes no no yes NoChange NoChange NoChange NoChange NoChange NoChange NoChange 0
NAK Out/premature status In
Status In/extra Out 0 1 1 Stall ignore ignore TX 0 NoChange NoChange NoChange
Control Read
Normal In/premature status Out 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Out Out Out Out Out In Out Out Out Out Out In Out Out Out 2 2 !=2 > 10 x x 2 2 !=2 > 10 x x 2 2 !=2 UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC valid valid valid x invalid x valid valid valid x invalid x valid valid valid 1 0 updates UC UC UC 1 0 updates UC UC UC 1 0 updates 1 1 1 UC UC UC 1 1 1 UC UC UC 1 1 1 updates updates updates UC UC UC updates updates updates UC UC UC updates updates updates UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 UC UC UC UC UC 1 UC UC UC 1 1 1 UC UC UC 1 1 1 UC UC UC 1 1 1 1 UC UC UC UC 1 1 UC UC UC UC UC 1 UC UC NoChange 0 0 ACK yes yes yes no no yes yes yes yes no no yes yes yes yes 0 1 1 Stall 0 1 1 Stall ignore ignore
NoChange NoChange 1
1 1 0 ACK (back) ACK
Nak In/premature status Out NoChange 0 0 0 1 1 Stall 0 1 1 Stall ignore ignore NAK ACK
NoChange NoChange NoChange NoChange 0 0
Status Out/extra In 0 1 1 Stall 0 1 1 Stall
Document #: 38-08001 Rev. **
Page 38 of 48
CY7C64013 CY7C64113
Table 19-3. Details of Modes for Differing Traffic Conditions (see Table 19-2 for the decode legend) (continued) End Point Mode
3 0 0 0 2 0 0 0 1 1 1 1 0 0 0 0 token Out Out In count > 10 x x buffer UC UC UC dval x invalid x DTOG UC UC UC DVAL UC UC UC COUNT UC UC UC PID Setup UC UC UC In UC 1 1 Out UC UC UC ACK UC UC UC
Set End Point Mode
3 2 1 0 response ignore ignore int no no yes NoChange NoChange 0
0 1 1 Stall
Out endpoint
Normal Out/erroneous In 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Out Out Out In In <= 10 > 10 x x x data junk junk UC UC valid x invalid x x updates updates updates UC UC 1 updates 0 UC UC updates updates updates UC UC UC UC UC UC UC UC UC UC UC UC 1 1 1 UC UC 1 UC UC UC UC 1 0 0 0 ACK ignore ignore ignore (STALL[3] = 0) NoChange Stall (STALL[3] = 1) NAK Out/erroneous In 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 Out Out Out In Out In <= 10 > 10 x x x x UC UC UC UC updates UC valid x invalid x updates x UC UC UC UC updates UC UC UC UC UC updates UC UC UC UC UC updates UC UC UC UC UC UC UC UC UC UC UC UC UC 1 UC UC UC 1 UC UC UC UC UC 1 UC NoChange NoChange NoChange NoChange NoChange NoChange NAK ignore ignore ignore RX ignore yes no no no yes no no yes yes yes no NoChange NoChange NoChange
Isochronous endpoint (Out)
In endpoint
Normal In/erroneous Out 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 1 Out Out In Out In Out In x x x x x x x UC UC UC UC UC UC UC x x x x x x x UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC UC 1 UC 1 UC 1 UC UC UC UC UC UC UC UC UC 1 UC UC UC UC NoChange NoChange 1 ignore (STALL[3] = 0) stall (STALL[3] = 1) 1 0 0 ACK (back) ignore NAK ignore TX yes no yes no yes NAK In/erroneous Out NoChange NoChange NoChange NoChange no no
Isochronous endpoint (In)
Document #: 38-08001 Rev. **
Page 39 of 48
CY7C64013 CY7C64113
20.0 Sample Schematic
2.2 uF
GND
3.3V Regulator OUT IN
Vref 2.2 uF
0V USB-B Vbus DD+ GND SHELL Optional 4.7 nF 250VAC
XTALO .01 uF 22x2(Rext) Vref 1.5K (RUUP) D0D0+ Vcc .01 uF
Vbus
0V
Vref
0V
10M
6.000 MHz
XTALI GND GND Vpp
0V
0V
Document #: 38-08001 Rev. **
Page 40 of 48
CY7C64013 CY7C64113
21.0 Absolute Maximum Ratings
Storage Temperature ..........................................................................................................................................-65C to +150C Ambient Temperature with Power Applied .................................................................................................................0C to +70C Supply voltage on VCC relative to VSS .................................................................................................................... -0.5V to +7.0V DC Input Voltage........................................................................................................................................... -0.5V to +VCC+0.5V DC Voltage Applied to Outputs in High Z State ............................................................................................ -0.5V to +VCC+0.5V Power Dissipation ..............................................................................................................................................................500 mW Static Discharge Voltage ................................................................................................................................................... >2000V Latch-up Current ............................................................................................................................................................ >200 mA Max Output Sink Current into Port 0, 1, 2, 3, and DAC[1:0] Pins ...................................................................................... 60 mA Max Output Sink Current into DAC[7:2] Pins ...................................................................................................................... 10 mA
22.0
Electrical Characteristics
Parameter General Conditions 3.3V 5% No GPIO source current Note 5 Any pin | (D+)-(D-) | 0.2 0.8 0.8 0 V < Vin < 3.3 V In series with each USB pin -10 19 1.425 0 2.8 28 8.0 All ports, LOW to HIGH edge All ports, HIGH to LOW edge IOL = 3 mA IOL = 8 mA IOH = 1.9 mA (all ports 0,1,2,3) 2.4 20% 2% 2.5 2.0 20 10 21 1.575 100 3.6 0.3 44 24.0 40% 8% 0.4 2.0 Min. 3.15 -0.4 Max. 3.45 0.4 50 50 30 1 Unit V V mA A mA A V V V pF A k ms V V k VCC VCC V V V
fOSC = 6 MHz; Operating Temperature = 0 to 70C, VCC = 4.0V to 5.25V
VREF Vpp ICC ISB1 Iref Iil Vdi Vcm Vse Cin Ilo Rext RUUP tvccs VUOH VUOL ZO Rup VITH VH VOL VOH
Reference Voltage Programming Voltage (disabled) VCC Operating Current Supply Current--Suspend Mode VREF Operating Current Input Leakage Current USB Interface Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance Hi-Z State Data Line Leakage External USB Series Resistor Power On Reset VCC Ramp Rate USB Upstream Static Output High Static Output Low USB Driver Output Impedance General Purpose I/O (GPIO) Pull-up Resistance (typical 14 k) Input Threshold Voltage Input Hysteresis Voltage Port 0,1,2,3 Output Low Voltage Output High Voltage
External Upstream USB Pull-up Resistor 1.5 k 5%, D+ to VREG Linear ramp 0V to VCC[4] 15 k 5% to Gnd 1.5 k 5% to VREF Including Rext Resistor
Notes: 4. Power-on Reset occurs whenever the voltage on VCC is below approximately 2.5V. 5. This is based on transitions every 2 full-speed bit times on average.
Document #: 38-08001 Rev. **
Page 41 of 48
CY7C64013 CY7C64113
Parameter DAC Interface Rup Isink0(0) Isink0(F) Isink1(0) Isink1(F) Irange Tratio IsinkDAC Ilin DAC Pull-up Resistance (typical 14 k) DAC[7:2] Sink current (0) DAC[7:2] Sink current (F) DAC[1:0] Sink current (0) DAC[1:0] Sink current (F) Programmed Isink Ratio: max/min Tracking Ratio DAC[1:0] to DAC[7:2] DAC Sink Current Differential Nonlinearity Vout = 2.0V DC Vout = 2.0V DC Vout = 2.0V DC Vout = 2.0V DC Vout = 2.0V DC Vout = 2.0V DAC Port
[7] [6]
Conditions
Min. 8.0 0.1 0.5 1.6 8 4 14 1.6
Max. 24.0 0.3 1.5 4.8 24 6 22 4.8 0.6
Unit k mA mA mA mA
Vout = 2.0V DC
[8]
mA LSB
Notes: 6. Irange: Isinkn(15)/ Isinkn(0) for the same pin. 7. Tratio = Isink1[1:0](n)/Isink0[7:2](n) for the same n, programmed. 8. Ilin measured as largest step size vs. nominal according to measured full scale and zero programmed values.
Document #: 38-08001 Rev. **
Page 42 of 48
CY7C64013 CY7C64113
23.0 Switching Characteristics (fOSC = 6.0 MHz)
Description Clock Source fOSC tcyc tCH tCL trfs tffs trfmfs tdratefs tsink tRD tOED tOEZ tOEDR tWR tDSTB tSTBZ tSTBLE twatch Clock Rate Clock Period Clock HIGH time Clock LOW time USB Full Speed Signaling Transition Rise Time Transition Fall Time Rise / Fall Time Matching; (tr/tf) Full Speed Date Rate DAC Interface Current Sink Response Time HAPI Read Cycle Timing Read Pulse Width OE LOW to Data Valid
[10, 11] [11] [10, 11] [9]
Parameter
Min.
Max.
Unit
6 0.25% 166.25 0.45 tCYC 0.45 tCYC 4 4 90 12 0.25% 20 20 111 167.08
MHz ns ns ns
ns ns % Mb/s s ns
0.8
15 40 20 0 60
ns ns ns
OE HIGH to Data High-Z
OE LOW to Data_Ready Deasserted
HAPI Write Cycle Timing Write Strobe Width Data Valid to STB HIGH (Data Set-up Time) STB HIGH to Data High-Z (Data Hold Time) STB LOW to Latch_Empty Deasserted Timer Signals Watch Dog Timer Period 8.192 14.336 ms
[11] [11]
15 5 15 0 50
ns ns ns ns
[10, 11]
Notes: 9. Per Table 7-6 of revision 1.1 of USB specification. 10. For 25-pF load. 11. Assumes chip select CS is asserted (LOW).
Document #: 38-08001 Rev. **
Page 43 of 48
CY7C64013 CY7C64113
tCYC tCH
CLOCK
tCL Figure 23-1. Clock Timing
tr
D+ 90% 10% D- 90%
tr
10%
Figure 23-2. USB Data Signal Timing
Interrupt Generated
Int
CS (P2.6, input)
tRD
OE (P2.5, input)
DATA (output)
D[23:0]
tOED
STB (P2.4, input) DReadyPin (P2.3, output)
(Shown for DRDY Polarity=0)
tOEZ
tOEDR
(Ready)
Internal Write
Internal Addr
Port0
Figure 23-3. HAPI Read by External Interface from USB Microcontroller
Document #: 38-08001 Rev. **
Page 44 of 48
CY7C64013 CY7C64113
Interrupt Generated CS (P2.6, input)
Int
tWR
STB (P2.4, input)
tSTBZ
DATA (input) D[23:0]
tDSTB
OE (P2.5, input)
tSTBLE
LEmptyPin (P2.2, output)
(Shown for LEMPTY Polarity=0)
(not empty)
Internal Read
Internal Addr
Port0
Figure 23-4. HAPI Write by External Device to USB Microcontroller
Document #: 38-08001 Rev. **
Page 45 of 48
CY7C64013 CY7C64113
24.0 Ordering Information
Ordering Code CY7C64013-SC CY7C64013-PC CY7C64113-PVC PROM Size 8 KB 8 KB 8 KB Package Name S21 P21 O48 Package Type 28-Pin (300-Mil) SOIC 28-Pin (300-Mil) PDIP 48-Pin (300-Mil) SSOP Operating Range Commercial Commercial Commercial
25.0
Package Diagrams
48-Lead Shrunk Small Outline Package O48
51-85061-B
28-Lead (300-Mil) Molded DIP P21
51-85014-B
Document #: 38-08001 Rev. **
Page 46 of 48
CY7C64013 CY7C64113
25.0 Package Diagrams (continued)
28-Lead (300-Mil) Molded SOIC S21
51-85026-A
Document #: 38-08001 Rev. **
Page 47 of 48
(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C64013 CY7C64113
Document Title: CY7C64013, CY7C64113 Full-Speed USB (12 Mbps) Function Document Number: 38-08001 REV. ** ECN NO. 109962 Issue Date 12/16/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00626 to 38-08001
Document #: 38-08001 Rev. **
Page 48 of 48

▲Up To Search▲

Price & Availability of CY7C64013

	To Download CY7C64013 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .